ADIS16IMU5SLASHPCBZ datasheet(22/46 Pages) AD

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Data Sheet

ADIS16575/ADIS16576/ADIS16577

THEORY OF OPERATION

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and compare it with the 16-bit checksum value provided in the burst

read. For an example of how to calculate the checksum, refer to the

SPI Checksum (SPI_CHKSUM) section.

DEVICE CONFIGURATION

Each configuration register contains 16 bits (two bytes). Bits[7:0]

contain the low byte, and Bits[15:8] contain the high byte of each

(see Table 13). Updating the contents of a register requires writing

to both bytes in the following sequence: low byte first and high byte

second.

The three parts to coding an SPI command (see Table 13) that

writes a new byte of data to a register include the following:

1. The write bit ( R/W = 1),

2. The address of the byte, [A6:A0],

3. The new data for that location, [DC7:DC0].

For example, Figure 58 shows a coding example for writing 0x0004

to the FILT_CTRL register (see Table 116). The 0xDC04 command

writes 0x04 to Address 0x5C (the lower byte), and the 0xDD00

command writes 0x00 to Address 0x5D (the upper byte).

Figure 58. SPI Sequence for Writing 0x0004 to FILT_CTRL

Note that writing to the control registers may trigger internal proc-

essing on the ADIS16575/ADIS16576/ADIS16577. The new regis-

ter value may not be available immediately for readback until this

processing is complete, and the value is fully applied. Consider this

behavior when verifying register writes.

Memory Structure

Figure 59 shows a functional diagram for the dual memory structure

of the ADIS16575/ADIS16576/ADIS16577. The flash memory bank

contains the operational code, unit-specific calibration coefficients,

and user configuration settings. The static random access memory

(SRAM) supports high-speed, real-time operation. Two copies of

this data reside in flash memory for redundancy and error recovery.

During initialization (power application or reset recovery), the firm-

ware loads the most recent copy of the configuration data from the

flash memory into the SRAM, which supports all normal operation,

including register access through the SPI.

Writing to a configuration register using the SPI updates the corre-

sponding SRAM location but does not automatically update the

settings in the flash memory bank. To save these settings to flash

memory, the manual flash memory update command (Register

GLOB_CMD, Bit 3, see Table 128) must be used. This command

updates both copies of the data in the flash memory sequentially,

ensuring that at least one valid copy is always available.

Registers that have flash memory backup display Yes in the Flash

Backup column of Table 13.

During power-on or reset recovery, the ADIS16575/ADIS16576/

ADIS16577 perform a CRC on the factory register data and user

to determine which copy of the register data to load. If a CRC

mismatch is detected, the memory error bit in the DIAG_STAT

operational code itself; corruption in the code also results in the

MEM bit being set in the DIAG_STAT register.

Figure 59. SRAM and Flash Memory Diagram

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