ADIS16IMU5SLASHPCBZ datasheet(39/46 Pages) AD

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Data Sheet

ADIS16575/ADIS16576/ADIS16577

USER REGISTER DEFINITIONS

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Bits[3:2] is 00 (binary), which places the ADIS16575/ADIS16576/

ADIS16577 in internal clock mode. In this mode, an internal clock

controls inertial sensor data acquisition and processing at a nominal

rate of 2000 Hz (4 kHz if SYNC_4KHZ is enabled). All sensors

are sampled at the IMU sample rate, ensuring synchronized data

collection across the system.

Scaled Sync Mode

When Register MSC_CTRL, Bits[3:2] = 10, the ADIS16575/

ADIS16576/ADIS16577 operate in scaled sync mode, supporting

a frequency range of 0.8 Hz to 400 Hz for the clock signal on

the SYNC pin. This mode is advantageous for synchronizing data

processing with signals from other systems, such as a Global

Navigation Satellite Systems (GNSS) PSS signal. In scaled sync

mode, the sample clock frequency is determined by the product

of the external clock scale factor (KECSF), set in the UP_SCALE

clock signal on the SYNC pin.

For example, to set up a sample rate of 2000 SPS using a 1

Hz input signal, configure the UP_SCALE register with a value of

0x07D0, which corresponds to a KECSF value of 2000 in decimal.

This configuration results in a sample rate of 2000 SPS for both the

inertial sensors and the signal processing. To achieve this setup,

send the sequence 0xE2D0 followed by 0xE307 to the DIN pin.

Table 121. UP_SCALE Register Definition

Addresses

Default

Access

Flash Backup

0x62, 0x63

0x07D0

R/W

Yes

Table 122. UP_SCALE Bit Definitions

Bits

Description

[15:0]

KECSF; binary format

Output Sync Mode

When Register MSC_CTRL, Bits[3:2] = 11, the ADIS16575/

ADIS16576/ADIS16577 operate in output sync mode, which is the

same as internal clock mode with one exception: the SYNC pin

pulses when the internal processor collects data from the inertial

sensors. Figure 72 provides an example of this signal.

Figure 72. Sync Output Signal, Register MSC_CTRL, Bits[3:2] = 11

Data Update Rate in External Sync Modes

When using the input sync option in scaled sync mode (Register

MSC_CTRL, Bits[3:2] = 10, see Table 120), the ODR is equal to

(fSYNC × KECSF)/(DEC_RATE + 1)

where:

fSYNC is the clock signal frequency on the SYNC pin.

KESCF is the value from the UP_SCALE register (see Table 122).

In direct sync mode, the UP_SCALE register is not used, and the

ODR directly follows the frequency of the external sync signal on

the SYNC pin without any scaling.

DECIMATION FILTER (DEC_RATE)

Table 123. DEC_RATE Register Definition

Addresses

Default

Access

Flash Backup

0x64, 0x65

0x0000

R/W

Yes

Table 124. DEC_RATE Bit Definitions

Bits

Description

[15:11]

Don’t care

[10:0]

Decimation rate, binary format, maximum = 1999

The DEC_RATE register (see Table 123 and Table 124) gives users

control over the averaging decimating filter. This filter averages

and decimates the data from the gyroscope and accelerometer,

and it also extends the tracking time between each update for

the delta angle and delta velocity. When operating the ADIS16575/

ADIS16576/ADIS16577 in the default internal clock mode (refer to

the Bits[3:2] in Table 120), users can calculate the nominal ODR

using the following formula:

fS/(DEC_RATE + 1)

where fS is the unit user-selected (2000 or 4000) sample rate. For

example, to lower the output sample rate to 100 SPS (2000 ÷ 20),

set the DEC_RATE to 0x0013. To do this setting, send the following

sequence to the DIN pin: first 0xE413, then 0xE500.

CONTINUOUS BIAS ESTIMATION

(NULL_CNFG)

Table 125. NULL_CNFG Register Definition

Addresses

Default

Access

Flash Backup

0x66, 0x67

0x070A

R/W

Yes

Table 126. NULL_CNFG Bit Definitions

Bits

Description

[15:14]

Not used

Z-axis accelerometer bias correction enable (1 = enabled)

Y-axis accelerometer bias correction enable (1 = enabled)

X-axis accelerometer bias correction enable (1 = enabled)

Z-axis gyroscope bias correction enable (1 = enabled)

Y-axis gyroscope bias correction enable (1 = enabled)

X-axis gyroscope bias correction enable (1 = enabled)

[7:4]

Not used

[3:0]

Time base control (TBC), range: 0 to 12 (default = 10); tB = 2TBC/fS,

fS = the internal sample clock frequency (either 2000 Hz or 4000 Hz

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