ADIS16IMU5SLASHPCBZ datasheet(18/46 Pages) AD

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Data Sheet

ADIS16575/ADIS16576/ADIS16577

THEORY OF OPERATION

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Rev. 0 | 18 of 46

Figure 68 for more details on the user calibration options available

for the gyroscopes.

The factory calibration of the accelerometer applies the following

correction formulas to the data of each accelerometer:

aXCaYCaZC = m11m12m13

m21m22m23

m31m32m33 ×

aXaYaZ + bXbYbZ +

0 p12p13

p21 0 p23

p31p32 0 ×

ω2XCω2YCω2

where:

aXC, aYC, and aZC are the accelerometer outputs (post calibration).

m11, m12, m13, m21, m22, m23, m31, m32, and m33 provide scale and

alignment correction.

aX, aY, and aZ are the accelerometer outputs (precalibration).

bX, bY, and bZ provide bias correction.

p12, p13, p21, p23, p31, and p32 provide a point of percussion

alignment correction (see Figure 71).

ω2XC, ω2YC, and ω2ZC are the square of the gyroscope outputs

(post calibration).

All of the correction factors in this relationship come from direct

observation of the response of each accelerometer at multiple

temperatures over the calibration temperature range (−40°C ≤ TC

≤ +85°C). These correction factors are stored in the flash memory

bank, but these factors are not available for observation or config-

uration. Register MSC_CTRL, Bit 6 (see Table 120) provides the

only user configuration option for the factory calibration of the accel-

erometers: an on/off control for the point of percussion, alignment

function. See Figure 69 for more details on the user calibration

options available for the accelerometers.

Bartlett Window FIR Filter

The Bartlett window finite impulse response (FIR) filter (see Figure

44) contains two averaging filter stages in a cascade configuration.

The FILT_CTRL register (see Table 116) provides the configuration

controls for this filter.

Figure 44. Bartlett Window FIR Filter Signal Path

Averaging and Decimating Filter

The second digital filter averages multiple samples together to

produce each register update. In this type of filter structure, the

number of samples in the average is equal to the reduction in the

update rate for the output data registers. The DEC_RATE register

(see Table 124) provides the configuration controls for this filter.

Figure 45. Averaging and Decimating Filter Diagram

All communication between the ADIS16575/ADIS16576/ADIS16577

and an external processor involves either reading the contents of

an output register or writing configuration or command information

to a control register. The output data registers include the latest

sensor data, error flags, and identification information. The control

registers include sample rate, filtering, calibration, and diagnostic

options. Each user accessible register has two bytes (upper and

lower), each of which has a unique address. See Table 13 for a

detailed list of all user registers and their corresponding addresses.

Figure 46. Basic Operation of the ADIS16575/ADIS16576/ADIS16577

SPI

The SPI provides access to the user registers (see Table 13).

Figure 47 shows the most common connections between the

ADIS16575/ADIS16576/ADIS16577 and an SPI main device, which

is often an embedded processor with an SPI-compatible interface.

In this example, the SPI main uses an interrupt service routine to

collect data every time the data ready (DR) signal pulses.

Additional information on the SPI of the ADIS16575/ADIS16576/

ADIS16577 can be found in the SPI Operation section.

Figure 47. Electrical Connection Diagram

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