ADIS16IMU5SLASHPCBZ datasheet(36/46 Pages) AD

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Data Sheet

ADIS16575/ADIS16576/ADIS16577

USER REGISTER DEFINITIONS

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Figure 69. User Calibration Signal Path, Accelerometers

Note that these registers can be programmed directly for immedi-

ate bias adjustment or set by using the CBE and bias update

command.

Calibration, Accelerometer Bias

(YA_BIAS_LWR and YA_BIAS_UPR)

Table 105. YA_BIAS_LWR Register Definition

Addresses

Default

Access

Flash Backup

0x50, 0x51

0x0000

R/W

Yes

Table 106. YA_BIAS_LWR Bit Definitions

Bits

Description

[15:0]

Y-axis accelerometer offset correction; lower word

Table 107. YA_BIAS_UPR Register Definition

Addresses

Default

Access

Flash Backup

0x52, 0x53

0x0000

R/W

Yes

Table 108. YA_BIAS_UPR Bit Definitions

Bits

Description

[15:0]

Y-axis accelerometer offset correction, upper word

The YA_BIAS_LWR (see Table 105 and Table 106) and

YA_BIAS_UPR (see Table 107 and Table 108) registers combine

to allow users to adjust the bias of the y-axis accelerometers. The

data format examples in Table 33 also apply to the YA_BIAS_UPR

the 32-bit combination of the YA_BIAS_LWR and YA_BIAS_

UPR registers. These registers influence the y-axis accelerometer

measurements in the same manner that the XA_BIAS_LWR and

XA_BIAS_UPR registers influence the x-axis accelerometer meas-

urements (see Figure 69).

Calibration, Accelerometer Bias

(ZA_BIAS_LWR and ZA_BIAS_UPR)

Table 109. ZA_BIAS_LWR Register Definition

Addresses

Default

Access

Flash Backup

0x54, 0x55

0x0000

R/W

Yes

Table 110. ZA_BIAS_LWR Bit Definitions

Bits

Description

[15:0]

Z-axis accelerometer offset correction; lower word

Table 111. ZA_BIAS_UPR Register Definition

Addresses

Default

Access

Flash Backup

0x56, 0x57

0x0000

R/W

Yes

Table 112. ZA_BIAS_UPR Bit Definitions

Bits

Description

[15:0]

Z-axis accelerometer offset correction, upper word

The ZA_BIAS_LWR (see Table 109 and Table 110) and ZA_BIAS_

UPR (see Table 111 and Table 112) registers combine to allow

users to adjust the bias of the z-axis accelerometers. The data

format examples in Table 33 also apply to the ZA_BIAS_UPR regis-

ter and the data format examples in Table 34 apply to the 32-bit

combination of the ZA_BIAS_LWR and ZA_BIAS_UPR registers.

These registers influence the z-axis accelerometer measurements

in the same manner that the XA_BIAS_LWR and XA_BIAS_UPR

registers influence the x-axis accelerometer measurements (see

Figure 69).

FIFO CONTROL (FIFO_CTRL) AND

WATERMARK INTERRUPT

The output FIFO control register (Address 0x5A and Address 0x5B)

configure the IMU output mode, FIFO overflow behavior, and water-

mark interrupt properties.

Table 113. FIFO_CTRL Register Definition

Address

Default

Access

Flash Backup

0x5A, 0x5B

N/A

R/W

Yes

Table 114. FIFO_CTRL Bit Definitions

Bits

Name

Description

[15:4]

WM_LVL

Watermark Threshold Level. Defines the number of

samples that must be enqueued into the FIFO to

trigger the watermark interrupt. A value of 0 means

the watermark triggers once a single sample is

enqueued.

WM_POL

Watermark Interrupt Polarity.

0 = active low.

1 = active high.

WM_EN

Watermark Interrupt Enable.

0 = disabled.

1 = enabled.

OVERFLO

Output FIFO Overflow Behavior.

0 = stop enqueueing.

1 = overwrite oldest.

FIFO_EN

Output FIFO Mode Enable.

0 = direct output mode.

1 = FIFO output mode.

The FIFO_CTRL register configures the IMU output mode,

FIFO overflow behavior, and watermark interrupt properties. The

ADIS16575/ADIS16576/ADIS16577 IMU supports the following two

output modes:

►

Direct Output Mode. Inertial sample data is loaded directly to the

output registers after processing. The data-ready signal pulses to

indicate fresh data availability.

ADIS16IMU5/PCBZ Datasheet(PDF) 36 Page - Analog Devices

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