ADIS16IMU5SLASHPCBZ datasheet(19/46 Pages) AD

19 / 46 page

Data Sheet

ADIS16575/ADIS16576/ADIS16577

THEORY OF OPERATION

analog.com

Rev. 0 | 19 of 46

Table 11. Generic Host Processor Pin Names and Functions

Mnemonic

Function

Device select

SCLK

Serial clock

MOSI

Host output, peripheral input

MISO

Host input, peripheral output

IRQ

Interrupt request

Embedded processors typically use control registers to configure

their serial ports for communicating with SPI serial devices, such

as the ADIS16575/ADIS16576/ADIS16577. Table 12 provides a

list of settings that describe the SPI protocols of the ADIS16575/

ADIS16576/ADIS16577. The initialization routine of the central

processor typically establishes these settings using firmware com-

mands to write parameters such as SPI mode, clock polarity

(CPOL), clock phase (CPHA), bit order, and clock frequency into

the control registers, ensuring proper communication between the

processor and the IMU.

Table 12. Generic Master Processor SPI Settings

Processor Setting

Description

Host Controller

IMU operates as peripheral

SCLK ≤ 15 MHz1

Maximum serial clock rate

SPI Mode 3

CPOL = 1 (polarity), CPHA = 1 (phase)

MSB First Mode

Bit sequence, see Figure 53 for coding

16-Bit Mode

Shift register and data length

1 A burst mode read requires this value to be ≤8 MHz (see Table 7 for more

information).

The factory default configuration provides users with a DR signal

on the DR pin (see Table 10) that pulses when the output data

registers update. Connect the DR pin to a pin on the embedded

processor to trigger data collection on the second edge of this

pulse. Register MSC_CTRL, Bit 0 (see Table 120), controls the

polarity of this signal. In Figure 48, Register MSC_ CTRL, Bit 0 =

1, meaning data collection must start on the rising edges of the DR

pulses.

Figure 48. Data Ready When Register MSC_CTRL, Bit 0 = 1 (Default)

During the start-up and reset recovery processes, the DR signal

may exhibit transient behavior before data production begins. Fig-

ure 49 shows an example of the DR behavior during startup, and

Figure 50 and Figure 51 provide examples of the DR behavior

during recovery from reset commands.

Figure 49. Data Ready Response During Startup

Figure 50. Data Ready Response During Reset (Register GLOB_CMD, Bit 7 =

1) Recovery

Figure 51. Data Ready Response During Reset (RST = 0) Recovery

ADIS16IMU5/PCBZ Datasheet(PDF) 19 Page - Analog Devices

ADIS16IMU5/PCBZ Datasheet(HTML) 19 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Datasheet Download

Link URL