ADIS16IMU5SLASHPCBZ datasheet(38/46 Pages) AD

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Data Sheet

ADIS16575/ADIS16576/ADIS16577

USER REGISTER DEFINITIONS

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Rev. 0 | 38 of 46

Table 120. MSC_CTRL Bit Definitions (Continued)

Bits

Name

Description

Setting SENS_BW = 1 reprograms the sensor filters

to 370 Hz, increasing the group delay by 0.17 ms for

gyroscopes and 0.63 ms for accelerometers.

SYNC_4KHZ

4 kHz Internal Sync Enable Bit. By default, the IMU

internal sample clock operates at 2 kHz.

0 = 2 kHz internal sample clock.

1 = 4 kHz internal sample clock.

For 2 kHz operation with improved noise performance,

set SYNC_4KHZ = 0 and enable a single average

decimation filter (DEC_RATE = 1).

TS_32

Timestamp Bit Width. This bit controls the width of the

timestamp register.

0 = 16-bit timestamp with 49.02 µs/LSB resolution.

1 = 32-bit timestamp with 0.01923 µs/LSB resolution.

BURST_32

32-Bit Burst Mode Enable. This bit enables 32-bit

inertial outputs within the burst stream. The user must

wait for a complete DR cycle before the burst array

updates with the intended data type.

0 = 16-bit outputs.

1 = 32-bit inertial outputs in burst stream.

OUT_SEL

Output Selection: Chooses the specific type of inertial

data transmitted during a burst read or added to the

FIFO when operating in FIFO mode.

0 = the output incorporates gyroscope and

accelerometer readings (default).

1 = the output comprises delta angle and delta velocity

measurements.

GSEN_EN

G-Sensitivity Compensation Enable. This bit applies

factory-calibrated linear acceleration (g-sensitivity)

compensation data to the gyroscope outputs.

0 = disable.

1 = enable.

POP_EN

Point of Percussion Enable. This bit adjusts the

acceleration sensors to a common point of percussion

on the package corner, taking into account angular

rotations on all three axes.

0 = disable.

1 = enable.

Reserved (do not use).

[3:2]

SYNC_M1 and

SYNC_M0

Sync Mode Selection: Enables the synchronization

mode.

00 = the internal clock drives the system sampling in

the internal sync mode. The SYNC_4KHZ bit in the

MSC_CTRL sets the internal clock rate to either 2 kHz

or 4 kHz.

01 = direct external sync mode, where the system

sample rate directly follows an external clock source

with sync enabled as an input. For ideal operation,

provide a 4 kHz sync input to maintain system

synchronization. Only a single edge of the pulse is used

for detection; therefore, the duty cycle can vary.

Table 120. MSC_CTRL Bit Definitions (Continued)

Bits

Name

Description

10 = eternal sync mode with UP_SCALE, translating an

external clock into an internal system sample rate.

11 = the internal sync drives the sampling clock, and the

sync signal operates as an output.

SYNC_POL

Sync Polarity. This bit determines the sync signal

behavior when used as an input or output.

For an external sync (input),

1 = rising edge sensitive.

0 = falling edge sensitive.

For an internal sync output),

1 = sampling is taking place.

0 = sampling is not taking place.

DR_POL

Data-Ready Polarity. This bit determines the stability of

the output data.

1 = the output data is stable when the DR pin is logic

high.

0 = the output data is stable when the DR pin is logic

low.

Point of Percussion

control for the point of percussion alignment function, which maps

the accelerometer sensors to the corner of the package shown in

Figure 71. The factory default setting in the MSC_CTRL register

activates this function. To turn this function off while retaining the

rest of the factory default settings in the MSC_CTRL register, set

sequence on the DIN pin: 0xE041, then 0xE100.

Figure 71. Point of Percussion Reference Point

Internal Clock Mode

ent configuration options for controlling the clock (fSM; see Figure

42 and Figure 43), which controls data acquisition and processing

for the inertial sensors. The default setting for Register MSC_CTRL,

ADIS16IMU5/PCBZ Datasheet(PDF) 38 Page - Analog Devices

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