ADIS16IMU5SLASHPCBZ datasheet(29/46 Pages) AD

29 / 46 page

Data Sheet

ADIS16575/ADIS16576/ADIS16577

USER REGISTER DEFINITIONS

analog.com

Rev. 0 | 29 of 46

Table 45. Z_ACCL_LWR Bit Definitions

Bits

Description

[15:0]

Z-axis accelerometer data; low word; additional resolution bits

Table 46. Z_ACCL_UPR Register Definition

Addresses

Default

Access

Flash Backup

0x1A, 0x1B

Not applicable

Table 47. Z_ACCL_UPR Bit Definitions

Bits

Description

[15:0]

Z-axis accelerometer data, high word; twos complement, 0 g =

0x0000, 1 LSB = 1/KA (see Table 35 for KA)

The Z_ACCL_LWR (see Table 44 and Table 45) and Z_ACCL_UPR

(see Table 46 and Table 47) registers contain the accelerometer

data for the z-axis.

INTERNAL TEMPERATURE (TEMP)

Table 48. TEMP Register Definition

Addresses

Default

Access

Flash Backup

0x1C, 0x1D

Not applicable

Table 49. TEMP Bit Definitions

Bits

Description

[15:0]

Temperature data; twos complement, 1 LSB = 0.1°C, 0°C = 0x0000

The TEMP register (see Table 48 and Table 49) provides a

coarse measurement of the temperature inside of the ADIS16575/

ADIS16576/ADIS16577. This data is most helpful in monitoring

relative changes in the thermal environment.

Table 50. TEMP Data Format Examples

Temperature (°C)

Decimal

Hexadeci

mal

Binary

+105

+1050

0x041A

0000 0100 0001 1010

+25

+250

0x00FA

0000 0000 1111 1010

+0.2

0x0002

0000 0000 0000 0010

+0.1

0x0001

0000 0000 0000 0001

0x0000

0000 0000 0000 0000

+0.1

−1

0xFFFF

1111 1111 1111 1111

+0.2

−2

0xFFFE

1111 1111 1111 1110

−40

−400

0xFE70

1111 1110 0111 0000

TIMESTAMP (TIME_STAMP_LWR AND

TIME_STAMP_UPR)

Table 51. TIME_STAMP_LWR and TIME_STAMP_UPR Register Definition

Addresses

Default

Access

Flash Backup

0x1E, 0x1F

Not applicable

0x20, 0x21

Not applicable

The sample timestamp 32-bit output register represents the time-

stamp of the current inertial sample relative to the external sync

edge.

The timestamp represents the delay between the internal interpola-

tion pulse for the sample and the user-provided external sync edge.

The timestamp functionality is active in all four sync modes:

►

Internal sync and output sync: the timestamp is a free-running

timer.

►

Direct external sync: the timestamp measures the delay between

the external sync clock and the corresponding internal interpola-

tion pulse.

►

Scaled external sync: the timestamp measures the latency from

the previous external sync edge to the internal interpolation

pulse of the current sample.

The resolution of this register depends on the TS_32 bit in the

MSC_CTRL register (see Bit 10 in Table 120). By default, TS_32

is cleared, giving the timestamp a resolution of 49.02 μs/LSB and

limiting the TIME_STAMP bit width to 16 bits. If TS_32 is set, all 32

bits of the TIME_STAMP register are utilized, with a resolution of

0.01923 μs/LSB. If the decimation filter is enabled, the timestamp

contains the time associated with the last sample in each data

update.

As an example, if UP_SCALE = 20, DEC_RATE = 0, TS_32 = 0,

and the external SYNC rate is 100 Hz, the result is the following

timestamp sequence: 0 LSB, 10 LSB, 21 LSB, 31 LSB, 41 LSB,

51 LSB, 61 LSB, 72 LSB, …, 194 LSB for the 20th sample, which

translates to 0 μs, 490 μs, …, 9510 μs and is the time from the

previous sync edge.

Another example, if TS_32 = 1, UP_SCALE = 20, DEC_RATE =

0, and an external SYNC rate of 100 Hz the result is the following

timestamp sequence: 0 LSB, 26000 LSB, 52000 LSB, 78000 LSB,

104000 LSB, 130000 LSB, 156000 LSB, 182000 LSB, …, 494000

LSB for the 20th sample, which translates to 0 μs, 500 μs, 1000 μs,

1500 μs, 2000 μs, 2500 μs, 3000 μs, 3500 μs, …, 9500 μs and is

the time from the previous sync edge.

DATA UPDATE COUNTER (DATA_CNTR)

Table 52. DATA_CNTR Register Definition

Addresses

Default

Access

Flash Backup

0x22, 0x23

Not applicable

Table 53. DATA_CNTR Bit Definitions

Bits

Description

[15:0]

Data update counter, offset binary format

When the ADIS16575/ADIS16576/ADIS16577 go through the pow-

er-on sequence or when these devices recover from a reset com-

mand, DATA_CNTR (see Table 52 and Table 53) starts with a

value of 0x0000 and increments every time new data loads into

the output registers. When the DATA_CNTR value hits 0xFFFF, the

next data update makes it wrap back around to 0x0000, where the

data continues to increase each time new data loads into the output

registers.

ADIS16IMU5/PCBZ Datasheet(PDF) 29 Page - Analog Devices

ADIS16IMU5/PCBZ Datasheet(HTML) 29 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46

Datasheet Download

Link URL