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XM33C321ASPZR Datasheet(PDF) 56 Page - Texas Instruments |
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XM33C321ASPZR Datasheet(HTML) 56 Page - Texas Instruments |
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56 / 122 page  7.10.2.3 I2C Timing Diagram SDA SCL tSU,DAT tHD,STA tHD,STA tVD,DAT tSU,STO tBUF tSU,STA tSP ttHIGHt ttLOWt tHD,DAT Figure 7-3. I2C Timing Diagram 7.10.3 SPI 7.10.3.1 SPI over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT SPI fSPI SPI clock frequency VDD ≥ 2.7V, HSIO 40(4) MHz VDD ≥ 1.71V, HSIO 23 MHz VDD ≥ 2.7V, SDIO 25 MHz VDD ≥ 1.71V, SDIO 20 MHz DCSCK SCK Duty Cycle 40 50 60 % Controller tSCLK_H/L SCLK High or Low time (tSPI/2) - 1 tSPI / 2 (tSPI/2) + 1 ns tCS.LEAD CS lead-time, CS active to clock SPH=0 1 SPI Clock ns SPH=1 1/2 SPI Clock ns tCS.LAG CS lag time, Last clock to CS inactive 1 SPI Clock ns tCS.ACC CS access time, CS active to PICO data out 1/2 SPI Clock ns tCS.DIS CS disable time, CS inactive to PICO high inpedance 1 SPI Clock ns tSU.CI POCI input data setup time (1) Delayed sampling enabled 1 ns tHD.CI POCI input data hold time VDD ≥ 2.7V, delayed sampling enabled 20 ns VDD ≥ 1.71V, delayed sampling enabled 25 ns tSU.CI POCI input data setup time (1) VDD ≥ 2.7V, no delayed sampling 18 ns VDD ≥ 1.71V, no delayed sampling 24 ns tHD.CI POCI input data hold time no delayed sampling enabled 0 ns tVALID.CO PICO output data valid time (2) 10 ns tHD.CO PICO output data hold time (3) 6 ns Peripheral tCS.LEAD CS lead-time, CS active to clock VDD ≥ 2.7V 19 ns VDD ≥ 1.71V 22 ns tCS.LAG CS lag time, Last clock to CS inactive 1 ns MSPM33C321A, MSPM33C3219 SLASFB6A – DECEMBER 2025 – REVISED SEPTEMBER 2026 www.ti.com 56 Submit Document Feedback Copyright © 2026 Texas Instruments Incorporated Product Folder Links: MSPM33C321A MSPM33C3219 |
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