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XM33C321ASPZR Datasheet(PDF) 57 Page - Texas Instruments |
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XM33C321ASPZR Datasheet(HTML) 57 Page - Texas Instruments |
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57 / 122 page  over operating free-air temperature range (unless otherwise noted) PARAMETERS TEST CONDITIONS MIN TYP MAX UNIT tCS.ACC CS access time, CS active to POCI data out VDD ≥ 2.7V 25 ns VDD ≥ 1.71V 31 ns tCS.DIS CS disable time, CS inactive to POCI high impedance VDD ≥ 2.7V 39 ns VDD ≥ 1.71V 41.5 ns tSU.PI PICO input data setup time 7 ns tHD.PI PICO input data hold time 0 ns tVALID.PO POCI output data valid time(2) VDD ≥ 2.7V 19 ns VDD ≥ 1.71V 24 ns tHD.PO POCI output data hold time(3) 5 ns (1) The POCI input data setup time can be fully compensated when delayed sampling feature is enabled. (2) Specifies the time to drive the next valid data to the output after the output changing SCLK clock edge (3) Specifies how long data on the output is valid after the output changing SCLK clock edge (4) The max SPI clock frequency when SPI is configured as a controller and transmitting only. 7.10.3.2 SPI Timing Diagram SCLK (SPO = 0) POCI SCLK (SPO = 1) CS (inverted) CS PICO tCS, LEAD tCS, ACC tCS, LAG tCS, DIS tSU,CI tHD,CI tVALID,CO tHD,CO 1 / fSPI tSCLK_H/L tSCLK_H/L Controller Mode, SPH = 0 CS (inverted) CS tCS, LEAD tCS, ACC tCS, LAG tCS, DIS tSU,CI tHD,CI tVALID,CO tHD,CO SCLK (SPO = 0) POCI SCLK (SPO = 1) PICO 1 / fSPI tSCLK_H/L tSCLK_H/L Controller Mode, SPH = 1 Figure 7-4. SPI Timing Diagram - Controller Mode www.ti.com MSPM33C321A, MSPM33C3219 SLASFB6A – DECEMBER 2025 – REVISED SEPTEMBER 2026 Copyright © 2026 Texas Instruments Incorporated Submit Document Feedback 57 Product Folder Links: MSPM33C321A MSPM33C3219 |
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