XM33C321ASPZR datasheet(61/122 Pages) TI2

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over recommended ranges of supply voltage and operating free-air temperature (unless otherwise noted)

PARAMETER

TEST CONDITIONS(1)

MIN

TYP

MAX

UNIT

Input capacitance

VOH

High level output voltage

SDIO

VDD≥2.7V, IIO=–6mA

VDD≥1.71V, IIO=–2mA

VDD-0.4

HSIO

VDD≥2.7V, DRV=1, IIO=–6mA

VDD≥1.71V, DRV=1, IIO=–3mA

VDD-0.4

VDD≥2.7V, DRV=0, IIO=–4mA

VDD≥1.71V, DRV=0, IIO=–2mA

VDD-0.4

HDIO

VDD≥2.7V, DRV=1, IIO=–20mA

VDD≥1.71V, DRV=1, IIO=–10mA

VDD-0.4

VDD≥2.7V, DRV=0, IIO=–6mA

VDD≥1.71V, DRV=0, IIO=–2mA

VDD-0.4

VOL

Low level output voltage

SDIO

VDD≥2.7V, IIO=6mA

VDD≥1.71V, IIO=2mA

0.4

HSIO

VDD≥2.7V, DRV=1, IIO=6mA

VDD≥1.71V, DRV=1, IIO=3mA

0.4

VDD≥2.7V, DRV=0, IIO=4mA

VDD≥1.71V, DRV=0, IIO=2mA

0.4

HDIO

VDD≥2.7V, DRV=1, IIO=20mA

VDD≥1.71V, DRV=1, IIO=10mA

0.4

VDD≥2.7V, DRV=0, IIO=6mA

VDD≥1.71V, DRV=0, IIO=2mA

0.4

Switching Characteristics

fmax

Port output frequency

SDIO (1)

VDD ≥ 2.7V, CL= 20pF

MHz

VDD ≥ 1.71V, CL= 20pF

HSIO

VDD ≥ 2.7V, DRV = 1, CL= 20pF

VDD ≥ 2.7V, DRV = 0, CL= 20pF

VDD ≥ 1.71V, DRV = 1, CL= 20pF

VDD ≥ 1.71V, DRV = 0, CL= 20pF

HDIO

VDD ≥ 2.7V, DRV = 1(5), CL= 20pF

VDD ≥ 2.7V, DRV = 0, CL= 20pF

VDD ≥ 1.71V, DRV = 1(5), CL= 20pF

VDD ≥ 1.71V, DRV = 0, CL= 20pF

tr,tf

Output rise/fall time

SDIO

VDD ≥ 2.7V, CL = 20pF

3.5

VDD ≥ 1.71V, CL = 20pF

6.6

HSIO

VDD ≥ 2.7V, DRV = 1, CL = 20pF

1.8

VDD ≥ 2.7V, DRV = 0, CL = 20pF

5.9

VDD ≥ 1.71V, DRV = 1, CL = 20pF

3.7

VDD ≥ 1.71V, DRV = 0, CL = 20pF

12.6

HDIO

VDD ≥ 2.7V, DRV = 1, CL = 20pF

1.7

VDD ≥ 2.7V, DRV = 0, CL = 20pF

3.8

VDD ≥ 1.71V, DRV = 1, CL = 20pF

3.1

VDD ≥ 1.71V, DRV = 0, CL = 20pF

8.2

(1)

The sum of the |IIO| current sourced or sunk by the device must always respect the absolute maximum rating

(2)

The leakage current is measured with VSS or VDD applied to the corresponding pin(s), unless otherwise noted.

(3)

The leakage of the digital port pins is measured individually. The port pin is selected for input and the pullup/pulldown resistor is

disabled.

(4)

This value is for SDIO not muxed with any analog inputs. If the SDIO is muxed with analog inputs then the leakage can be higher.

(5)

When operating a HDIO in DRV=1 high drive strength configuration, a series resistor is necessary to limit the signal slew rate

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MSPM33C321A, MSPM33C3219

SLASFB6A – DECEMBER 2025 – REVISED SEPTEMBER 2026

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