XM33C321ASPZR datasheet(88/122 Pages) TI2

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8.16.1 Timers (TIMx)

The timer peripherals in these devices support the following key features, for specific configuration see Table

8-18:

Specific features for the general-purpose timer (TIMGx) include:

• 16-bit and 32-bit timers with up, down or up-down counting modes, with repeat-reload mode

• Selectable and configurable clock source

• 8-bit programmable prescaler to divide the counter clock frequency

• Two independent CC channels for

– Output compare

– Input capture

– PWM output

– One-shot mode

• Shadow CC register available in TIMG4_n (n = 0, 1, 2, 3) and TIMG12_0

• Shadow load register available in TIMG4_n (n = 0, 1, 2, 3)

• Support quadrature encoder interface (QEI) for positioning and movement sensing available in TIMG8_n (n =

0, 1)

• Support synchronization and cross trigger among different timer instances in the same power domain

• Support interrupt/DMA trigger generation and cross peripherals trigger capability

• Cross trigger event logic for Hall sensor inputs TIMG8_n (n = 0, 1)

Specific features for the advanced timer (TIMA0_x) include:

• 16-bit timer with up, down or up-down counting modes, with repeat-reload mode

• Selectable and configurable clock source

• 8-bit programmable prescaler to divide the counter clock frequency

• Repeat counter to generate an interrupt or event only after a given number of cycles of the counter

• Up to four independent CC channels for

– Output compare

– Input capture

– PWM output

– One-shot mode

• Internal 5th and 6th internal CC channel for capture/compare events

• Shadow register for load and CC register available in both TIMA0_0 and TIMA0_1

• Complementary output PWM

• Asymmetric PWM with programmable dead band insertion

• Fault handling mechanism to ensure the output signals in a safe user-defined state when a fault condition is

encountered

• Support synchronization and cross trigger among different TIMx instances in the same power domain

• Support interrupt and DMA trigger generation and cross peripherals (such as ADC) trigger capability

• Two additional capture/compare channels for internal events

Table 8-18. TIMx Configurations

TIMER

NAME

POWER

DOMAIN

RESOLUTION

PRESCALE

REPEAT

COUNTER

CAPTURE /

COMPARE

CHANNELS

PHASE

LOAD

SHADOW

LOAD

SHADOW

DEADBAND

FAULT

QEI

TIMA0_0

PD1

16-bit

8-bit

4 + 2

Yes

–

TIMA0_1

PD1

16-bit

8-bit

4 + 2

Yes

–

TIMG4_0

PD0

16-bit

8-bit

–

Yes

–

TIMG4_1

PD0

16-bit

8-bit

–

Yes

–

TIMG4_2

PD1

16-bit

8-bit

–

Yes

–

TIMG4_3

PD1

16-bit

8-bit

–

Yes

–

TIMG8_0

PD1

16-bit

8-bit

–

Yes

TIMG8_1

PD1

16-bit

8-bit

–

Yes

MSPM33C321A, MSPM33C3219

SLASFB6A – DECEMBER 2025 – REVISED SEPTEMBER 2026

www.ti.com

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