TMS320F241FN datasheet(38/66 Pages) TI

38 / 66 page

TMS320C242

DSP CONTROLLER

SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

watchdog (WD) timer module

The ’C242 device includes a watchdog (WD) timer module. The WD function of this module monitors software

and hardware operation by generating a system reset if it is not periodically serviced by software by having the

correct key written. The WD timer operates independently of the CPU and is always enabled. It does not need

any CPU initialization to function. When a system reset occurs, the WD timer defaults to the fastest WD timer

rate available (6.55 ms for a 39 062.5-Hz WDCLK signal). As soon as reset is released internally, the CPU starts

executing code, and the WD timer begins incrementing. This means that, to avoid a premature reset, WD setup

should occur early in the power-up sequence. See Figure 12 for a block diagram of the WD module. The WD

module features include the following:

D WD Timer

–

Seven different WD overflow rates ranging from 6.55 ms to 1 s

–

A WD-reset key (WDKEY) register that clears the WD counter when a correct value is written, and

generates a system reset if an incorrect value is written to the register

–

WD check bits that initiate a system reset if an incorrect value is written to the WD control register

(WDCR)

D Automatic activation of the WD timer, once system reset is released

–

Three WD control registers located in control register frame beginning at address 7020h.

NOTE: All registers in this module are 8-bit registers. When a register is accessed, the register data is in the lower byte, the upper byte is read

as zeros. Writing to the upper byte has no effect.

Figure 12 shows the WD block diagram. Table 11 shows the different WD overflow (timeout) selections.

TMS320F241FN Datasheet(PDF) 38 Page - Texas Instruments