TMS320F241FN datasheet(10/66 Pages) TI

10 / 66 page

TMS320C242

DSP CONTROLLER

SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

architectural overview

The functional block diagram provides a high-level description of each component in the ’C242 DSP controllers.

The TMS320x24x devices are composed of three main functional units: a ’C2xx DSP core, internal memory,

and peripherals. In addition to these three functional units, there are several system-level features of the ’C242

that are distributed. These system features include the memory map, device reset, interrupts, digital

input / output (I / O), clock generation, and low-power operation.

system-level functions

device memory map

The ’C242 device implements three separate address spaces for program memory, data memory, and

I/O space. On the ’C242, the first 96 (0–5Fh) data memory locations are either allocated for memory-mapped

registers or reserved. This memory-mapped register space contains various control and status registers,

including those for the CPU.

All the on-chip peripherals of the ’C242 devices are mapped into data memory space. Access to these registers

is made by the CPU instructions addressing their data memory locations. Figure 1 shows the ’C242 memory

map.

TMS320F241FN Datasheet(PDF) 10 Page - Texas Instruments