TMS320F241FN datasheet(6/66 Pages) TI

6 / 66 page

TMS320C242

DSP CONTROLLER

SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

Terminal Functions - ’C242 PG and FN Packages

NAME

64-PIN

QFP

68-PIN

PLCC

TYPE†

RESET

STATE‡

DESCRIPTION

NAME

NO.

TYPE†

STATE‡

DESCRIPTION

INTERFACE CONTROL SIGNALS

WDDIS

Watchdog disable. Note that on ROM devices, only the WDDIS function

is valid. If the input is low, the watchdog timer cannot be disabled in the

software. If the input is high, the watchdog timer can be disabled in the

software through the WDDIS bit in the WDCR register.

ANALOG-TO-DIGITAL CONVERTER (ADC) INPUTS

ADCIN00

ADCIN01

ADCIN02

ADCIN03

Analog inputs to the ADC

ADCIN04

Analog inputs to the ADC

ADCIN05

ADCIN06

ADCIN07

VCCA

–

Analog supply voltage for ADC (5 V). VCCA must be isolated from

digital supply voltage.

VSSA

–

Analog ground reference for ADC

VREFHI

–

ADC analog high-voltage reference input

VREFLO

–

ADC analog low-voltage reference input

EVENT MANAGER

T1CMP/T1PWM/

IOPB4

I/O/Z

Timer 1 compare output/general-purpose bidirectional digital I/O (GPIO).

T2CMP/T2PWM/

IOPB5

I/O/Z

Timer 2 compare output/GPIO

TDIR/

IOPB6

I/O

Counting direction for GP timer/GPIO. If TDIR=1, upward counting is

selected. If TDIR=0, downward counting is selected.

TCLKIN/

IOPB7

I/O

External clock input for GP timer/GPIO. Note that timer can also use

the internal device clock.

CAP1/QEP0/

IOPA3

I/O

Capture input #1/quadrature encoder pulse input #0/GPIO

CAP2/QEP1/

IOPA4

I/O

Capture input #2/quadrature encoder pulse input #1/GPIO

CAP3/

IOPA5

I/O

Capture input #3/GPIO

PWM1/

IOPA6

I/O/Z

Compare/PWM output pin #1 or GPIO

PWM2/

IOPA7

I/O/Z

Compare/PWM output pin #2 or GPIO

PWM3/

IOPB0

I/O/Z

Compare/PWM output pin #3 or GPIO

PWM4/

IOPB1

I/O/Z

Compare/PWM output pin #4 or GPIO

PWM5/

IOPB2

I/O/Z

Compare/PWM output pin #5 or GPIO

PWM6/IOPB3

I/O/Z

Compare/PWM output pin #6 or GPIO

PDPINT

Power drive protection interrupt input. This interrupt, when activated, puts

the PWM output pins in the high-impedance state, should motor

drive/power converter abnormalities, such as overvoltage or overcurrent,

etc., arise. PDPINT is a falling-edge-sensitive interrupt. After the falling

edge, this pin must be held low for two clock cycles for the core to

recognize the interrupt.

† I = input, O = output, Z = high impedance

‡ The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is

an output, its level at reset is indicated.

§ These pins are internally pulled high. However, these pins are not pulled high in the emulation devices (’F243/’F241).

NOTE:

Bold, italicized pin names indicate pin function after reset.

TMS320F241FN Datasheet(PDF) 6 Page - Texas Instruments

TMS320F241FN Datasheet(HTML) 6 Page - Texas Instruments

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