TMS320F241FN datasheet(22/66 Pages) TI

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TMS320C242

DSP CONTROLLER

SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

external interrupts

The ’C242 device has four external interrupts. These interrupts include:

D XINT1. The XINT1 control register (at 7070h) provides control and status for this interrupt. XINT1 can be used

as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or as a general-purpose I/O pin. XINT1

can also be programmed to trigger an interrupt on either the rising or the falling edge.

D XINT2. The XINT2 control register (at 7071h) provides control and status for this interrupt. XINT2 can be used

as a high-priority (Level 1) or low-priority (Level 6) maskable interrupt or a general-purpose I/O pin. XINT2 can

also be programmed to trigger an interrupt on either the rising or the falling edge.

D NMI. This is a nonmaskable external interrupt.

D PDPINT. This interrupt is provided for safe operation of power converters and motor drives controlled by

the ’C242. This maskable interrupt can put the timers and PWM output pins in high-impedance states and

inform the CPU in case of motor drive abnormalities such as overvoltage, overcurrent, and excessive

temperature rise. PDPINT is a Level 1 interrupt.

Table 6 is a summary of the external interrupt capability of the ’C242.

Table 6. External Interrupt Types and Functions

EXTERNAL

INTERRUPT

CONTROL

NAME

CONTROL

ADDRESS

MASKABLE?

XINT1

XINT1CR

7070h

Yes

(Level 1 or 6)

XINT2

XINT2CR

7071h

Yes

(Level 1 or 6)

NMI

—

PDPINT

EVIMRA

742Ch

Yes

(Level 1)

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