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TMS320F241FN Datasheet(PDF) 8 Page - Texas Instruments |
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TMS320F241FN Datasheet(HTML) 8 Page - Texas Instruments |
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8 / 66 page  TMS320C242 DSP CONTROLLER SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999 8 POST OFFICE BOX 1443 • HOUSTON, TEXAS 77251–1443 Terminal Functions - ’C242 PG and FN Packages (Continued) NAME 64-PIN QFP 68-PIN PLCC TYPE† RESET STATE‡ DESCRIPTION NAME NO. NO. TYPE† STATE‡ DESCRIPTION CLOCK SIGNALS (CONTINUED) CLKOUT/IOPD0 5 12 I/O O Clock output. This pin outputs the CPU clock (CLKOUT) only. This pin can be used as a GPIO, if it is not used as a clock output pin. TEST SIGNALS TCK 28 36 I I JTAG test clock with internal pullup TDI 29 37 I I JTAG test data input (TDI) with internal pullup. TDI is clocked into the selected register (instruction or data) on a rising edge of TCK. TDO 30 38 O O JTAG scan out, test data output (TDO). The contents of the selected register (instruction or data) is shifted out of TDO on the falling edge of TCK. TMS 31 39 I I JTAG test-mode select (TMS) with internal pullup. This serial control input is clocked into the TAP controller on the rising edge of TCK. TRST 32 40 I I JTAG test reset with internal pulldown. TRST, when driven high, gives the scan system control of the operations of the device. If this signal is not connected or driven low, the device operates in its functional mode, and the test reset signals are ignored. EMU0 37 48 I/O I Emulator I/O pin 0 with internal pullup. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through the JTAG scan. EMU1 38 49 I/O I Emulator I/O pin 1 with internal pullup. When TRST is driven high, this pin is used as an interrupt to or from the emulator system and is defined as input/output through JTAG scan. SUPPLY SIGNALS V 9 16 – – Digital logic supply voltage (5 V) VDD 41 52 – – Digital logic supply voltage (5 V) – 42 – – V 1 8 – – Digital logic and buffer supply voltage (5 V) VDDO 34 45 – – Digital logic and buffer supply voltage (5 V) 51 62 – – – 41 – – VSS 10 17 – – Digital logic ground reference VSS 40 51 – – Digital logic ground reference – 43 – – 2 9 – – VSSO 26 34 – – Digital logic and buffer ground reference VSSO 33 44 – – Digital logic and buffer ground reference 50 61 – – NO CONNECT NC – 27 No internal connection made to this pin DNC 25 33 – – Do not connect. Reserved for test. † I = input, O = output, Z = high impedance ‡ The reset state indicates the state of the pin at reset. If the pin is an input, indicated by an I, its state is determined by user design. If the pin is an output, its level at reset is indicated. § These pins are internally pulled high. However, these pins are not pulled high in the emulation devices (’F243/’F241). NOTE: Bold, italicized pin names indicate pin function after reset. |
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