TMS320F241FN datasheet(48/66 Pages) TI

48 / 66 page

TMS320C242

DSP CONTROLLER

SPRS063B – DECEMBER 1997 – REVISED DECEMBER 1999

POST OFFICE BOX 1443

• HOUSTON, TEXAS 77251–1443

external reference crystal/clock with PLL circuit enabled

timings with the PLL circuit enabled

PARAMETER

MIN

TYP

MAX

UNIT

Input clock frequency

Oscillator/Resonator

MHz

Input clock frequency

CLKIN

MHz

C1, C2

Load capacitance

switching characteristics over recommended operating conditions [H = 0.5 tc(CO)] (see Figure 18)

PARAMETER

CLOCK MODE

MIN

TYP

MAX

UNIT

tc(CO)

Cycle time, CLKOUT

tf(CO)

Fall time, CLKOUT

tr(CO)

Rise time, CLKOUT

tw(COL)

Pulse duration, CLKOUT low

H–3

H+3

tw(COH)

Pulse duration, CLKOUT high

H–3

H+3

Transition time, PLL synchronized after PLL enabled

before PLL lock,

CLKIN multiply by 4

2500tc(Cl)

timing requirements (see Figure 18)

EXTERNAL REFERENCE

CRYSTAL

MIN

MAX

UNIT

tc(Cl)

Cycle time†, XTAL1/CLKIN

5 MHz

200

tf(Cl)

Fall time, XTAL1/CLKIN

tr(Cl)

Rise time, XTAL1/CLKIN

tw(CIL)

Pulse duration, XTAL1/CLKIN low as a percentage of tc(Cl)

tw(CIH)

Pulse duration, XTAL1/CLKIN high as a percentage of tc(Cl)

† This device utilizes a fully static design and, therefore, can operate with input clock cycle time [tc(CI)] approaching infinity. The device is

characterized at frequencies approaching 0 Hz, but is tested at fclk = 6.7 MHz to meet device test time requirements.

NOTE: Timings assume CLKOUT is set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset.Timings assume CLKOUT is

set to output CPUCLK. CLKOUT is initialized to CPUCLK by power-on reset.

XTAL1/CLKIN

CLKOUT

tc(CI)

tw(CIL)

tw(CIH)

tf(Cl)

tr(Cl)

tw(COL)

tw(COH)

tc(CO)

tr(CO)

tf(CO)

Figure 18. CLKIN-to-CLKOUT Timing for PLL Oscillator Mode, Multiply-by-4 Option with 5-MHz Clock

TMS320F241FN Datasheet(PDF) 48 Page - Texas Instruments

TMS320F241FN Datasheet(HTML) 48 Page - Texas Instruments

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