 |
Electronic Components Datasheet Search |
|
|
Electronic Components Datasheet Search |
|
ATmega64A Datasheet(PDF) 86 Page - ATMEL Corporation |
|
|
|||||||||||||||||||||||||||||
ATmega64A Datasheet(HTML) 86 Page - ATMEL Corporation |
|
|
86 / 392 page  86 8160C–AVR–07/09 ATmega64A • TMS, ADC5 – Port F, Bit 5 ADC5, Analog to Digital Converter, Channel 5. TMS, JTAG Test mode Select: This pin is used for navigating through the TAP-controller state machine. When the JTAG interface is enabled, this pin can not be used as an I/O pin. • TCK, ADC4 – Port F, Bit 4 ADC4, Analog to Digital Converter, Channel 4. TCK, JTAG Test Clock: JTAG operation is synchronous to TCK. When the JTAG interface is enabled, this pin can not be used as an I/O pin. • ADC3 - ADC0 – Port F, Bit 3:0 Analog to Digital Converter, Channel 3:0. Table 13-19. Overriding Signals for Alternate Functions in PF7:PF4 Signal Name PF7/ADC7/TDI PF6/ADC6/TDO PF5/ADC5/TMS PF4/ADC4/TCK PUOE JTAGEN JTAGEN JTAGEN JTAGEN PUOV 101 1 DDOE JTAGEN JTAGEN JTAGEN JTAGEN DDOV 0 SHIFT_IR + SHIFT_DR 00 PVOE 0 JTAGEN 0 0 PVOV 0 TDO 0 0 DIEOE JTAGEN JTAGEN JTAGEN JTAGEN DIEOV 000 0 DI ––– – AIO TDI/ADC7 INPUT ADC6 INPUT TMS/ADC5 INPUT TCKADC4 INPUT |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |
New Zealand ▼
English
Chinese
German
Japanese
Russian
Korean
Spanish
French
Italian
Portuguese
Polish
Vietnamese
Indian
Mexican
British
New Zealand
