ATmega64A datasheet(99/392 Pages) ATMEL

99 / 392 page

8160C–AVR–07/09

ATmega64A

togram for illustrating the single-slope operation. The diagram includes non-inverted and

inverted PWM outputs. The small horizontal line marks on the TCNT0 slopes represent Com-

pare Matches between OCR0 and TCNT0.

Figure 14-6. Fast PWM Mode, Timing Diagram

The Timer/Counter Overflow Flag (TOV0) is set each time the counter reaches MAX. If the inter-

rupt is enabled, the interrupt handler routine can be used for updating the compare value.

In fast PWM mode, the compare unit allows generation of PWM waveforms on the OC0 pin. Set-

ting the COM01:0 bits to two will produce a non-inverted PWM and an inverted PWM output can

be generated by setting the COM01:0 to three (See Table 14-4 on page 107). The actual OC0

value will only be visible on the port pin if the data direction for the port pin is set as output. The

PWM waveform is generated by setting (or clearing) the OC0 Register at the Compare Match

between OCR0 and TCNT0, and clearing (or setting) the OC0 Register at the timer clock cycle

the counter is cleared (changes from MAX to BOTTOM).

The PWM frequency for the output can be calculated by the following equation:

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR0 Register represent special cases when generating a PWM

waveform output in the fast PWM mode. If the OCR0 is set equal to BOTTOM, the output will be

a narrow spike for each MAX+1 timer clock cycle. Setting the OCR0 equal to MAX will result in a

constantly high or low output (depending on the polarity of the output set by the COM01:0 bits.)

A frequency (with 50% duty cycle) waveform output in fast PWM mode can be achieved by set-

ting OC0 to toggle its logical level on each Compare Match (COM01:0 = 1). The waveform

generated will have a maximum frequency of f

oc0 = fclk_I/O/2 when OCR0 is set to zero. This fea-

ture is similar to the OC0 toggle in CTC mode, except the double buffer feature of the Output

Compare unit is enabled in the fast PWM mode.

TCNTn

OCRn Update and

TOVn Interrupt Flag Set

Period

OCn

(COMn1:0 = 2)

(COMn1:0 = 3)

OCRn Interrupt Flag Set

fOCnPWM

clk_I/O

N 256

⋅

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