ATmega64A datasheet(34/392 Pages) ATMEL

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8160C–AVR–07/09

ATmega64A

Wait until EEWE becomes zero.

Wait until SPMEN in SPMCSR becomes zero.

Write new EEPROM address to EEAR (optional).

Write new EEPROM data to EEDR (optional).

Write a logical one to the EEMWE bit while writing a zero to EEWE in EECR.

Within four clock cycles after setting EEMWE, write a logical one to EEWE.

The EEPROM can not be programmed during a CPU write to the Flash memory. The software

must check that the Flash programming is completed before initiating a new EEPROM write.

Step 2 is only relevant if the software contains a Boot Loader allowing the CPU to program the

Flash. If the Flash is never being updated by the CPU, step 2 can be omitted. See “Boot Loader

Support – Read-While-Write Self-programming” on page 281 for details about Boot

programming.

Caution: An interrupt between step 5 and step 6 will make the write cycle fail, since the

EEPROM Master Write Enable will time-out. If an interrupt routine accessing the EEPROM is

interrupting another EEPROM access, the EEAR or EEDR Register will be modified, causing the

interrupted EEPROM access to fail. It is recommended to have the Global Interrupt Flag cleared

during the four last steps to avoid these problems.

When the write access time has elapsed, the EEWE bit is cleared by hardware. The user soft-

ware can poll this bit and wait for a zero before writing the next byte. When EEWE has been set,

the CPU is halted for two cycles before the next instruction is executed.

• Bit 0 – EERE: EEPROM Read Enable

The EEPROM Read Enable Signal EERE is the read strobe to the EEPROM. When the correct

address is set up in the EEAR Register, the EERE bit must be written to a logic one to trigger the

EEPROM read. The EEPROM read access takes one instruction, and the requested data is

available immediately. When the EEPROM is read, the CPU is halted for four cycles before the

next instruction is executed.

The user should poll the EEWE bit before starting the read operation. If a write operation is in

progress, it is neither possible to read the EEPROM, nor to change the EEAR Register.

The calibrated Oscillator is used to time the EEPROM accesses. Table 7-5 lists the typical pro-

gramming time for EEPROM access from the CPU.

Note:

1. Uses 1 MHz clock, independent of CKSEL Fuse settings.

The following code examples show one assembly and one C function for writing to the

EEPROM. The examples assume that interrupts are controlled (e.g., by disabling interrupts

globally) so that no interrupts will occur during execution of these functions. The examples also

assume that no Flash boot loader is present in the software. If such code is present, the

EEPROM write function must also wait for any ongoing SPM command to finish.

Table 7-5.

EEPROM Programming Time

(1)

Symbol

Number of Calibrated RC Oscillator

Cycles

Typ Programming Time

EEPROM write (from CPU)

8448

8.4 ms

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