ATmega64A datasheet(93/392 Pages) ATMEL

93 / 392 page

8160C–AVR–07/09

ATmega64A

The Timer/Counter (TCNT0) and Output Compare Register (OCR0) are 8-bit registers. Interrupt

request (shorten as Int.Req.) signals are all visible in the Timer Interrupt Flag Register (TIFR).

All interrupts are individually masked with the Timer Interrupt Mask Register (TIMSK). TIFR and

TIMSK are not shown in the figure since these registers are shared by other timer units.

The Timer/Counter can be clocked internally, via the prescaler, or asynchronously clocked from

the TOSC1/2 pins, as detailed later in this section. The asynchronous operation is controlled by

the Asynchronous Status Register (ASSR). The Clock Select logic block controls which clock

source the Timer/Counter uses to increment (or decrement) its value. The Timer/Counter is inac-

tive when no clock source is selected. The output from the Clock Select logic is referred to as the

timer clock (clk

T0).

The double buffered Output Compare Register (OCR0) is compared with the Timer/Counter

value at all times. The result of the compare can be used by the Waveform Generator to gener-

ate a PWM or variable frequency output on the Output Compare pin (OC0). See “Output

Compare Unit” on page 94. for details. The Compare Match event will also set the Compare Flag

(OCF0) which can be used to generate an Output Compare interrupt request.

14.2.1

Definitions

Many register and bit references in this datasheet are written in general form. A lower case “n”

replaces the Timer/Counter number, in this case 0. However, when using the register or bit

defines in a program, the precise form must be used i.e. TCNT0 for accessing Timer/Counter0

counter value and so on.

The definitions in Table 14-1 are also used extensively throughout this section.

14.3

Timer/Counter Clock Sources

The Timer/Counter can be clocked by an internal synchronous or an external asynchronous

clock source. The clock source clk

T0 is by default equal to the MCU clock, clkI/O. When the AS0

bit in the ASSR Register is written to logic one, the clock source is taken from the Timer/Counter

Oscillator connected to TOSC1 and TOSC2. For details on asynchronous operation, see “ASSR

– Asynchronous Status Register” on page 108. For details on clock sources and prescaler, see

“Timer/Counter Prescaler” on page 105.

14.4

Counter Unit

The main part of the 8-bit Timer/Counter is the programmable bi-directional counter unit. Figure

14-2 shows a block diagram of the counter and its surrounding environment.

Table 14-1.

Definitions

BOTTOM

The counter reaches the BOTTOM when it becomes zero (0x00).

MAX

The counter reaches its MAXimum when it becomes 0xFF (decimal 255).

TOP

The counter reaches the TOP when it becomes equal to the highest value in the

count sequence. The TOP value can be assigned to be the fixed value 0xFF

(MAX) or the value stored in the OCR0 Register. The assignment is dependent

on the mode of operation.

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