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ATmega64A Datasheet(PDF) 91 Page - ATMEL Corporation |
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ATmega64A Datasheet(HTML) 91 Page - ATMEL Corporation |
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91 / 392 page ![]() 91 8160C–AVR–07/09 ATmega64A 13.4.18 PINF – Port F Input Pins Address Note that PORTF and DDRF Registers are not available in ATmega103 compatibility mode where Port F serves as digital input only. 13.4.19 PORTG – Port G Data Register 13.4.20 DDRG – Port G Data Direction Register 13.4.21 PING – Port G Input Pins Address Note that PORTG, DDRG, and PING are not available in ATmega103 compatibility mode. In the ATmega103 compatibility mode Port G serves its alternate functions only (TOSC1, TOSC2, WR, RD and ALE). 13.4.22 SFIOR – Special Function IO Register • Bit 2 – PUD: Pull-up disable When this bit is written to one, the pull-ups in the I/O ports are disabled even if the DDxn and PORTxn Registers are configured to enable the pull-ups ({DDxn, PORTxn} = 0b01). See “Con- figuring the Pin” on page 69 for more details about this feature. Bit 7 65 43 21 0 0x00 (0x20) PINF7 PINF6 PINF5 PINF4 PINF3 PINF2 PINF1 PINF0 PINF Read/Write RRR RR RR R Initial Value N/A N/A N/A N/A N/A N/A N/A N/A Bit 7 6 5 432 10 (0x65) – – – PORTG4 PORTG3 PORTG2 PORTG1 PORTG0 PORTG Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 65 43 21 0 (0x64) – – – DDG4 DDG3 DDG2 DDG1 DDG0 DDRG Read/Write R R R R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 Bit 7 65 43 21 0 (0x63) – – – PING4 PING3 PING2 PING1 PING0 PING Read/Write RRR RR RR R Initial Value 0 0 0 N/A N/A N/A N/A N/A Bit 7 654 3 2 1 0 0x20 (0x40) TSM – – – ACME PUD PSR0 PSR321 SFIOR Read/Write R/W R R R R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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