ATmega64A datasheet(46/392 Pages) ATMEL

46 / 392 page

8160C–AVR–07/09

ATmega64A

Power Management and Sleep Modes

Sleep modes enable the application to shut down unused modules in the MCU, thereby saving

power. The AVR provides various sleep modes allowing the user to tailor the power consump-

tion to the application’s requirements.

To enter any of the six sleep modes, the SE-bit in MCUCR must be written to logic one and a

SLEEP instruction must be executed. The SM2, SM1, and SM0 bits in the MCUCR Register

select which sleep mode (Idle, ADC Noise Reduction, Power-down, Power-save, Standby, or

Extended Standby) will be activated by the SLEEP instruction. See Table 9-2 for a summary. If

an enabled interrupt occurs while the MCU is in a sleep mode, the MCU wakes up. The MCU is

then halted for four cycles in addition to the start-up time, it executes the interrupt routine, and

resumes execution from the instruction following SLEEP. The contents of the Register File and

SRAM are unaltered when the device wakes up from sleep. If a reset occurs during sleep mode,

the MCU wakes up and executes from the Reset Vector.

Figure 8-1 on page 37 presents the different clock systems in the ATmega64A, and their distri-

bution. This figure is helpful in selecting an appropriate sleep mode.

9.1

Idle Mode

When the SM2:0 bits are written to 000, the SLEEP instruction makes the MCU enter Idle mode,

stopping the CPU but allowing SPI, USART, Analog Comparator, ADC, Two-wire Serial Inter-

face, Timer/Counters, Watchdog, and the interrupt system to continue operating. This sleep

mode basically halts clk

CPU and clkFLASH, while allowing the other clocks to run.

Idle mode enables the MCU to wake up from external triggered interrupts as well as internal

ones like the Timer Overflow and USART Transmit Complete interrupts. If wake-up from the

Analog Comparator interrupt is not required, the Analog Comparator can be powered down by

setting the ACD bit in the Analog Comparator Control and Status Register – ACSR. This will

reduce power consumption in Idle mode. If the ADC is enabled, a conversion starts automati-

cally when this mode is entered.

9.2

ADC Noise Reduction Mode

When the SM2:0 bits are written to 001, the SLEEP instruction makes the MCU enter ADC

Noise Reduction mode, stopping the CPU but allowing the ADC, the external interrupts, the

Two-wire Serial Interface address watch, Timer/Counter0 and the Watchdog to continue operat-

ing (if enabled). This sleep mode basically halts clk

I/O, clkCPU, and clk-FLASH, while allowing the

other clocks to run.

This improves the noise environment for the ADC, enabling higher resolution measurements. If

the ADC is enabled, a conversion starts automatically when this mode is entered. Apart form the

ADC Conversion Complete interrupt, only an External Reset, a Watchdog Reset, a Brown-out

Reset, a Two-wire Serial Interface address match interrupt, a Timer/Counter0 interrupt, an

SPM/EEPROM ready interrupt, an external level interrupt on INT7:4, or an External Interrupt on

INT3:0 can wake up the MCU from ADC Noise Reduction mode.

ATmega64A Datasheet(PDF) 46 Page - ATMEL Corporation

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