ATmega64A datasheet(19/392 Pages) ATMEL

19 / 392 page

8160C–AVR–07/09

ATmega64A

In ATmega103 compatibility mode, the first 4,096 data memory locations address both the Reg-

ister File, the I/O memory and the internal data SRAM. The first 32 locations address the

address the internal data SRAM.

An optional external data SRAM can be used with the ATmega64A. This SRAM will occupy an

area in the remaining address locations in the 64K address space. This area starts at the

address following the internal SRAM. The Register File, I/O, Extended I/O and internal SRAM

occupy the lowest 4,352 bytes in Normal mode, and the lowest 4,096 bytes in the ATmega103

compatibility mode (Extended I/O not present), so when using 64KB (65,536 bytes) of External

memory, 61,184 Bytes of External memory are available in Normal mode, and 61,440 Bytes in

ATmega103 compatibility mode. See “External Memory Interface” on page 23 for details on how

to take advantage of the external memory map.

When the addresses accessing the SRAM memory space exceeds the internal data memory

locations, the external data SRAM is accessed using the same instructions as for the internal

data memory access. When the internal data memories are accessed, the read and write strobe

pins (PG0 and PG1) are inactive during the whole access cycle. External SRAM operation is

enabled by setting the SRE bit in the MCUCR Register.

Accessing external SRAM takes one additional clock cycle per byte compared to access of the

internal SRAM. This means that the commands LD, ST, LDS, STS, LDD, STD, PUSH, and POP

take one additional clock cycle. If the Stack is placed in external SRAM, interrupts, subroutine

calls and returns take three clock cycles extra because the 2-byte Program Counter is pushed

and popped, and external memory access does not take advantage of the internal pipeline

memory access. When external SRAM interface is used with wait state, one-byte external

access takes two, three, or four additional clock cycles for one, two, and three wait states

respectively. Interrupt, subroutine calls and returns will need five, seven, or nine clock cycles

more than specified in the AVR Instruction Set manual for one, two, and three waitstates.

The five different addressing modes for the data memory cover: Direct, Indirect with Displace-

ment, Indirect, Indirect with Pre-decrement, and Indirect with Post-increment. In the Register

File, registers R26 to R31 feature the indirect addressing pointer registers.

The direct addressing reaches the entire data space.

The Indirect with Displacement mode reaches 63 address locations from the base address given

by the Y- or Z-register.

When using register indirect addressing modes with automatic pre-decrement and post-incre-

ment, the address registers X, Y, and Z are decremented or incremented.

The 32 general purpose working registers, 64 I/O Registers, 160 extended I/O Registers, and

the 4,096 bytes of internal data SRAM in the ATmega64A are all accessible through all these

addressing modes. The Register File is described in “General Purpose Register File” on page

12.

ATmega64A Datasheet(PDF) 19 Page - ATMEL Corporation