ATmega64A datasheet(101/392 Pages) ATMEL

101 / 392 page

101

8160C–AVR–07/09

ATmega64A

pare Match between OCR0 and TCNT0 when the counter increments, and setting (or clearing)

the OC0 Register at Compare Match between OCR0 and TCNT0 when the counter decrements.

The PWM frequency for the output when using phase correct PWM can be calculated by the fol-

lowing equation:

The N variable represents the prescale factor (1, 8, 32, 64, 128, 256, or 1024).

The extreme values for the OCR0 Register represent special cases when generating a PWM

waveform output in the phase correct PWM mode. If the OCR0 is set equal to BOTTOM, the out-

put will be continuously low and if set equal to MAX the output will be continuously high for non-

inverted PWM mode. For inverted PWM the output will have the opposite logic values.

At the very start of period 2 in Figure 14-7 OCn has a transition from high to low even though

there is no Compare Match. The point of this transition is to guarantee symmetry around BOT-

TOM. There are two cases that give a transition without Compare Match.

• OCR0 changes its value from MAX, like in Figure 14-7. When the OCR0 value is MAX the

OCn pin value is the same as the result of a down-counting Compare Match. To ensure

symmetry around BOTTOM the OCn value at MAX must correspond to the result of an up-

counting Compare Match.

• The timer starts counting from a higher value than the one in OCR0, and for that reason

misses the Compare Match and hence the OCn change that would have happened on the

way up.

14.8

Timer/Counter Timing Diagrams

Figure 14-8 and Figure 14-9 contain timing data for the Timer/Counter operation. The

Timer/Counter is a synchronous design and the timer clock (clk

T0) is therefore shown as a clock

enable signal. The figure shows the count sequence close to the MAX value. Figure 14-10 and

Figure 14-11 show the same timing data, but with the prescaler enabled. The figures illustrate

when interrupt flags are set.

The following figures show the Timer/Counter in synchronous mode, and the timer clock (clk

T0)

is therefore shown as a clock enable signal. In asynchronous mode, clk

I/O should be replaced by

the Timer/Counter Oscillator clock. The figures include information on when interrupt flags are

set. Figure 14-8 contains timing data for basic Timer/Counter operation. The figure shows the

count sequence close to the MAX value in all modes other than phase correct PWM mode.

Figure 14-8. Timer/Counter Timing Diagram, no Prescaling

fOCnPCPWM

clk_I/O

N 510

⋅

------------------

clk

(clk

I/O/1)

TOVn

clk

I/O

TCNTn

MAX - 1

MAX

BOTTOM

BOTTOM + 1

ATmega64A Datasheet(PDF) 101 Page - ATMEL Corporation

ATmega64A Datasheet(HTML) 101 Page - ATMEL Corporation

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL