ATmega64A datasheet(137/392 Pages) ATMEL

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137

8160C–AVR–07/09

ATmega64A

15.11.6

TCCR3C – Timer/Counter3 Control Register C

• Bit 7 – FOCnA: Force Output Compare for Channel A

• Bit 6 – FOCnB: Force Output Compare for Channel B

• Bit 5 – FOCnC: Force Output Compare for Channel C

The FOCnA/FOCnB/FOCnC bits are only active when the WGMn3:0 bits specifies a non-PWM

mode. When writing a logical one to the FOCnA/FOCnB/FOCnC bit, an immediate Compare

Match is forced on the waveform generation unit. The OCnA/OCnB/OCnC output is changed

according to its COMnx1:0 bits setting. Note that the FOCnA/FOCnB/FOCnC bits are imple-

mented as strobes. Therefore it is the value present in the COMnx1:0 bits that determine the

effect of the forced compare.

A FOCnA/FOCnB/FOCnC strobe will not generate any interrupt nor will it clear the timer in Clear

Timer on Compare match (CTC) mode using OCRnA as TOP.

The FOCnA/FOCnB/FOCnB bits are always read as zero.

• Bit 4:0 – Reserved Bits

These bits are reserved for future use. For ensuring compatibility with future devices, these bits

must be written to zero when TCCRnC is written.

15.11.7

TCNT1H and TCNT1L – Timer/Counter1

15.11.8

TCNT3H and TCNT3L – Timer/Counter3

The two Timer/Counter I/O locations (TCNTnH and TCNTnL, combined TCNTn) give direct

access, both for read and for write operations, to the Timer/Counter unit 16-bit counter. To

ensure that both the high and low bytes are read and written simultaneously when the CPU

accesses these registers, the access is performed using an 8-bit temporary High Byte Register

(TEMP). This temporary register is shared by all the other 16-bit registers. See “Accessing 16-bit

Registers” on page 114.

Modifying the counter (TCNTn) while the counter is running introduces a risk of missing a Com-

pare Match between TCNTn and one of the OCRnx Registers.

Writing to the TCNTn Register blocks (removes) the Compare Match on the following timer clock

for all compare units.

Bit

765

43210

(0x8C)

FOC3A

FOC3B

FOC3C

–––––

TCCR3C

Read/Write

RRRR

Initial Value

000

00000

Bit

765

43210

0x2D (0x4D)

TCNT1[15:8]

TCNT1H

0x2C (0x4C)

TCNT1[7:0]

TCNT1L

Read/Write

R/W

Initial Value

000

00000

Bit

765

43210

(0x89)

TCNT3[15:8]

TCNT3H

(0x88)

TCNT3[7:0]

TCNT3L

Read/Write

R/W

Initial Value

000

00000

ATmega64A Datasheet(PDF) 137 Page - ATMEL Corporation

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