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ATmega64A Datasheet(PDF) 157 Page - ATMEL Corporation |
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ATmega64A Datasheet(HTML) 157 Page - ATMEL Corporation |
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157 / 392 page ![]() 157 8160C–AVR–07/09 ATmega64A Figure 17-10. Timer/Counter Timing Diagram, Setting of OCF2, with Prescaler (f clk_I/O/8) Figure 17-11 shows the setting of OCF2 and the clearing of TCNT2 in CTC mode. Figure 17-11. Timer/Counter Timing Diagram, Clear Timer on Compare Match Mode, with Pres- caler (f clk_I/O/8) 17.9 Register Description 17.9.1 TCCR2 – Timer/Counter Control Register • Bit 7 – FOC2: Force Output Compare The FOC2 bit is only active when the WGM20 bit specifies a non-PWM mode. However, for ensuring compatibility with future devices, this bit must be set to zero when TCCR2 is written when operating in PWM mode. When writing a logical one to the FOC2 bit, an immediate Com- pare Match is forced on the waveform generation unit. The OC2 output is changed according to its COM21:0 bits setting. Note that the FOC2 bit is implemented as a strobe. Therefore it is the value present in the COM21:0 bits that determines the effect of the forced compare. OCFn OCRn TCNTn OCRn Value OCRn - 1 OCRn OCRn + 1 OCRn + 2 clk I/O clk Tn (clk I/O/8) OCFn OCRn TCNTn (CTC) TOP TOP - 1 TOP BOTTOM BOTTOM + 1 clk I/O clk Tn (clk I/O/8) Bit 7 6 5 4 3 210 0x25 (0x45) FOC2 WGM20 COM21 COM20 WGM21 CS22 CS21 CS20 TCCR2 Read/Write W R/W R/W R/W R/W R/W R/W R/W Initial Value 0 0 0 0 0 0 0 0 |
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