ATmega64A datasheet(201/392 Pages) ATMEL

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201

8160C–AVR–07/09

ATmega64A

21. TWI – Two-wire Serial Interface

21.1

Features

• Simple yet Powerful and Flexible Communication Interface, Only Two Bus Lines Needed

• Both Master and Slave Operation Supported

• Device can Operate as Transmitter or Receiver

• 7-bit Address Space allows up to 128 Different Slave Addresses

• Multi-master Arbitration Support

• Up to 400 kHz Data Transfer Speed

• Slew-rate Limited Output Drivers

• Noise Suppression Circuitry Rejects Spikes on Bus Lines

• Fully Programmable Slave Address with General Call Support

• Address Recognition Causes Wake-up when AVR is in Sleep Mode

21.2

Overview

The TWI module is comprised of several submodules, as shown in Figure 21-1. All registers

drawn in a thick line are accessible through the AVR data bus.

Figure 21-1. Overview of the TWI Module

Address Register

(TWAR)

Address Match Unit

Address Comparator

Control Unit

Control Register

(TWCR)

Status Register

(TWSR)

State Machine and

Status Control

SCL

Slew-rate

Control

Spike

Filter

SDA

Slew-rate

Control

Spike

Filter

Bit Rate Generator

Bit Rate Register

(TWBR)

Prescaler

Bus Interface Unit

START / STOP

Control

Arbitration Detection

Ack

Spike Suppression

Address/Data Shift

ATmega64A Datasheet(PDF) 201 Page - ATMEL Corporation

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