R5F562TADDFM datasheet(47/94 Pages) RENESAS

47 / 94 page

R01DS0096EJ0100 Rev.1.00

Page 47 of 92

Apr 20, 2011

RX62T Group

4. I/O Registers

0008 C4D0h

POE

Port output enable control register 4

POECR4

2 to 3PCLK*5

0008 C4D2h

POE

Port output enable control register 5

POECR5

2 to 3PCLK*5

0008 C4D4h

POE

Port output enable control register 6

POECR6

2 to 3PCLK*5

0008 C4D6h

POE

Input level control/status register 4

ICSR4

8, 16

2 to 3PCLK*5

0008 C4D8h

POE

Input level control/status register 5

ICSR5

8, 16

2 to 3PCLK*5

0008 C4DAh

POE

Active level setting register 1

ALR1

8, 16

2 to 3PCLK*5

0009 0200h

0009 03FFh

CAN0*4

Mailbox registers 0 to 31

MB0

MB 31

128

8, 16, 32

2 to 3PCLK*5

0009 0400h

CAN0*4

Mask register 0

MKR0

8, 16, 32

2 to 3PCLK*5

0009 0404h

CAN0*4

Mask register 1

MKR1

8, 16, 32

2 to 3PCLK*5

0009 0408h

CAN0*4

Mask register 2

MKR2

8, 16, 32

2 to 3PCLK*5

0009 040Ch

CAN0*4

Mask register 3

MKR3

8, 16, 32

2 to 3PCLK*5

0009 0410h

CAN0*4

Mask register 4

MKR4

8, 16, 32

2 to 3PCLK*5

0009 0414h

CAN0*4

Mask register 5

MKR5

8, 16, 32

2 to 3PCLK*5

0009 0418h

CAN0*4

Mask register 6

MKR6

8, 16, 32

2 to 3PCLK*5

0009 041Ch

CAN0*4

Mask register 7

MKR7

8, 16, 32

2 to 3PCLK*5

0009 0420h

CAN0*4

FIFO received ID compare register 0

FIDCR0

8, 16, 32

2 to 3PCLK*5

0009 0424h

CAN0*4

FIFO received ID compare register 1

FIDCR1

8, 16, 32

2 to 3PCLK*5

0009 0428h

CAN0*4

Mask invalid register

MKIVLR

8, 16, 32

2 to 3PCLK*5

0009 042Ch

CAN0*4

Mailbox interrupt enable register

MIER

8, 16, 32

2 to 3PCLK*5

0009 0820h

0009 083Fh

CAN0*4

Message control registers 0 to 31

MCTL0

MCTL31

2 to 3PCLK*5

0009 0840h

CAN0*4

Control register

CTLR

8, 16

2 to 3PCLK*5

0009 0842h

CAN0*4

Status register

STR

8, 16

2 to 3PCLK*5

0009 0844h

CAN0*4

Bit configuration register

BCR

8, 16, 32

2 to 3PCLK*5

0009 0848h

CAN0*4

Receive FIFO control register

RFCR

2 to 3PCLK*5

0009 0849h

CAN0*4

Receive FIFO pointer control register

RFPCR

2 to 3PCLK*5

0009 084Ah

CAN0*4

Transmit FIFO control register

TFCR

2 to 3PCLK*5

0009 084Bh

CAN0*4

Transmit FIFO pointer control register

TFPCR

2 to 3PCLK*5

0009 084Ch

CAN0*4

Error interrupt enable register

EIER

2 to 3PCLK*5

0009 084Dh

CAN0*4

Error interrupt factor judge register

EIFR

2 to 3PCLK*5

0009 084Eh

CAN0*4

Receive error count register

RECR

2 to 3PCLK*5

0009 084Fh

CAN0*4

Transmit error count register

TECR

2 to 3PCLK*5

0009 0850h

CAN0*4

Error code store register

ECSR

2 to 3PCLK*5

0009 0851h

CAN0*4

Channel search support register

CSSR

2 to 3PCLK*5

0009 0852h

CAN0*4

Mailbox search status register

MSSR

2 to 3PCLK*5

0009 0853h

CAN0*4

Mailbox search mode register

MSMR

2 to 3PCLK*5

0009 0854h

CAN0*4

Time stamp register

TSR

8, 16

2 to 3PCLK*5

0009 0856h

CAN0*4

Acceptance filter support register

AFSR

8, 16

2 to 3PCLK*5

0009 0858h

CAN0*4

Test control register

TCR

2 to 3PCLK*5

0009 4001h

LIN0

LIN wake-up baud rate select register

LWBR

2 to 3PCLK*5

0009 4002h

LIN0

LIN baud rate prescaler 0 register

LBRP0

8, 16

2 to 3PCLK*5

0009 4003h

LIN0

LIN baud rate prescaler 1 register

LBRP1

8, 16

2 to 3PCLK*5

Table 4.1

List of I/O Registers (Address Order) (14 / 23)

Address

Module

Abbreviation

Number

of Bits

Access

Size

Number of

Access

Cycles

R5F562TADDFM Datasheet(PDF) 47 Page - Renesas Technology Corp

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