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R5F562TADDFM Datasheet(PDF) 70 Page - Renesas Technology Corp |
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R5F562TADDFM Datasheet(HTML) 70 Page - Renesas Technology Corp |
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70 / 94 page  R01DS0096EJ0100 Rev.1.00 Page 70 of 92 Apr 20, 2011 RX62T Group 5. Electrical Characteristics Note: • tIICcyc: Cycles of internal base clock (IICφ) for the RIIC module Note 1. The value in parentheses is used when ICMR3.NF[1:0] are set to 11b while a digital filter is enabled with ICFER.NFE = 1. Note 2. Cb indicates the total capacity of the bus line. Table 5.9 Timing of On-Chip Peripheral Modules (2) Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = 40 to +85C. Ta is the same under conditions 1 to 3. Item Symbol Min.*1 *2 Max. Unit Test Conditions RIIC (standard mode) SCL input cycle time tSCL 6(12) t llCcyc + 1300 - ns Figure 5.10 SCL input high pulse width tSCLH 3(6) t llCcyc + 300 - ns SCL input low pulse width tSCLL 3(6) t llCcyc + 1000 - ns SCL, SDA input rising time tSr - 1000 ns SCL, SDA input falling time tSf - 300 ns SCL, SDA input spike pulse removal time tSP 01(4) t llCcyc ns SDA input bus free time tBUF 3(6) t llCcyc + 300 - ns Start condition input hold time tSTAH tllCcyc + 300 - ns Re-start condition input setup time tSTAS 1000 - ns Stop condition input setup time tSTOS 1000 - ns Data input setup time tSDAS tllCcyc + 50 - ns Data input hold time tSDAH 0- ns SCL, SDA capacitive load Cb - 400 pF RIIC (fast mode) SCL input cycle time tSCL 6(12) t llCcyc + 600 - ns SCL input high pulse width tSCLH 3(6) t llCcyc + 300 - ns SCL input low pulse width tSCLL 3(6) t llCcyc + 300 - ns SCL, SDA input rising time tSr 20 + 0.1Cb 300 ns SCL, SDA input falling time tSf 20 + 0.1Cb 300 ns SCL, SDA input spike pulse removal time tSP 01(4) t llCcyc ns SDA input bus free time tBUF 3(6) t llCcyc + 300 - ns Start condition input hold time tSTAH tllCcyc + 300 - ns Re-start condition input setup time tSTAS 300 - ns Stop condition input setup time tSTOS 300 - ns Data input setup time tSDAS tllCcyc + 50 - ns Data input hold time tSDAH 0- ns SCL, SDA capacitive load Cb - 400 pF |
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