R5F562TADDFM datasheet(84/94 Pages) RENESAS

84 / 94 page

R01DS0096EJ0100 Rev.1.00

Page 84 of 92

Apr 20, 2011

RX62T Group

5. Electrical Characteristics

5.6

Oscillation Stop Detection Timing

Figure 5.23

Oscillation Stop Detection Timing

Table 5.18

Oscillation Stop Detection Circuit Characteristics

Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.

Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC

Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC

Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC

Ta = -40 to +85°C. Ta is the same under conditions 1 to 3.

Item

Symbol

Min.

Typ.

Max.

Unit

Test

Conditions

Detection time

tdr

1.0

Figure 5.23

Internal oscillation frequency when

oscillation stop is detected

fMAIN

0.5

7.0

MHz

ICLK

Main clock oscillator

Internal oscillation

Normal operation

Abnormal operation

OSTDF*

Note : * This indicates the OSTDF flag in the oscillation detection control register (OSTDCR).

tdr

R5F562TADDFM Datasheet(PDF) 84 Page - Renesas Technology Corp

R5F562TADDFM Datasheet(HTML) 84 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL