Electronic Components Datasheet Search
  New Zealand  ▼
ALLDATASHEET.CO.NZ

X  

R5F562TADDFM Datasheet(PDF) 5 Page - Renesas Technology Corp

Part # R5F562TADDFM
Description  100-MHz 32-bit RX MCUs, FPU, 165 DMIPS, 12-bit ADC
PDF  94 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F562TADDFM Datasheet(HTML) 5 Page - Renesas Technology Corp

  R5F562TADDFM Datasheet HTML 1Page - Renesas Technology Corp R5F562TADDFM Datasheet HTML 2Page - Renesas Technology Corp R5F562TADDFM Datasheet HTML 3Page - Renesas Technology Corp R5F562TADDFM Datasheet HTML 4Page - Renesas Technology Corp R5F562TADDFM Datasheet HTML 5Page - Renesas Technology Corp R5F562TADDFM Datasheet HTML 6Page - Renesas Technology Corp R5F562TADDFM Datasheet HTML 7Page - Renesas Technology Corp R5F562TADDFM Datasheet HTML 8Page - Renesas Technology Corp R5F562TADDFM Datasheet HTML 9Page - Renesas Technology Corp Next Button
Zoom Inzoom in Zoom Outzoom out
 5 / 94 page
background image
R01DS0096EJ0100 Rev.1.00
Page 5 of 92
Apr 20, 2011
RX62T Group
1. Overview
Communications
CAN module (CAN)
(as an optional
function)
 1 channel
 32 mailboxes
Serial peripheral
interface (RSPI)
 1 unit
 RSPI transfer facility
Using the MOSI (master out, slave in), MISO (master in, slave out), SSL (slave select),
and RSPI clock (RSPCK) signals enables serial transfer through SPI operation (four
lines) or clock-synchronous operation (three lines)
Capable of handling serial transfer as a master or slave
 Data formats
Switching between MSB first and LSB first
The number of bits in each transfer can be changed to any number of bits from 8 to 16,
or to 20, 24, or 32 bits.
128-bit buffers for transmission and reception
Up to four frames can be transmitted or received in a single transfer operation (with each
frame having up to 32 bits)
 Buffered structure
 Double buffers for both transmission and reception
LIN module (LIN)
 1 channel (LIN master)
 Supports revisions 1.3, 2.0, and 2.1 of the LIN protocol
A/D converter
12-bit A/D converter
(S12ADA)
 12 bits (2 units x 4 channels)
 12-bit resolution
 Conversion time:
1.0
s per channel (in operation with A/D conversion clock ADCLK at 50 MHz) for AVCC
= 4.0 to 5.5 V
2.0
s per channel (in operation with A/D conversion clock ADCLK at 25 MHz) for
AVCC0 = 3.0 to 3.6 V
 Two basic operating modes
Single mode and scan mode
 Scan mode
One-cycle scan mode
Continuous scan mode
2-channel scan mode (Input ports of the A/D unit are divided into two groups in this
mode, and the activation sources are separately selectable for each group.)
 Sample-and-hold function
A common sample-and-hold circuit for both units is included.
Additionally, sample-and-hold circuit for each unit is included. (three channels per unit)
 A/D-conversion register settings for each input pin.
 Two registers for the result of conversion are provided for a single analog input pin of
each unit (AN000 and AN100).
 Three ways to start A/D conversion
Conversion can be started by software, a conversion start trigger from a timer (MTU3 or
GPT), or an external trigger signal.
 Functionality for 8- or 10-bit precision output
Right-shifting of the results of conversion for output by two or four bits is selectable.
 Self-diagnostic function
The self-diagnostic function internally generates three analog input voltages (VREFL0,
VREFH0 x 1/2, VREFH0).
 Amplification of input signals by a programmable gain amplifier (three channels per unit)
Amplification rate: 2.0-, 2.5-, 3.077-, 3.636-, 4.0-, 4.444-, 5.0-, 5.714-, 6.667-, 10.0-, or
13.333-times amplification (a total of 11 steps)
 Window comparators (three channels per unit)
Table 1.1
Outline of Specifications (4 / 5)
Classification
Module/Function
Description



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com