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R5F562TADDFM Datasheet(PDF) 77 Page - Renesas Technology Corp |
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R5F562TADDFM Datasheet(HTML) 77 Page - Renesas Technology Corp |
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77 / 94 page ![]() R01DS0096EJ0100 Rev.1.00 Page 77 of 92 Apr 20, 2011 RX62T Group 5. Electrical Characteristics Figure 5.18 GPT Input/Output Timing Note: • tPcyc: PCLK cycle Figure 5.19 POE3# Clock Timing Table 5.12 Timing of On-Chip Peripheral Modules (5) Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = -40 to +85°C. Ta is the same under conditions 1 to 3. Item Symbol Min. Max. Unit Test Conditions POE3 POE# input pulse width tPOEW 1.5 - tPcyc Figure 5.19 Input capture input ICLK tGTICW POEn# input PCLK tPOEW |
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