R5F562TADDFM datasheet(86/94 Pages) RENESAS

86 / 94 page

R01DS0096EJ0100 Rev.1.00

Page 86 of 92

Apr 20, 2011

RX62T Group

5. Electrical Characteristics

5.8

Data Flash (Flash Memory for Data Storage) Characteristics

Note 1. Definition of rewrite/erase cycle:

The rewrite/erase cycle is the number of erasing for each block. When the rewrite/erase cycle is n times (n = 30000), erasing can

be performed n times for each block. For instance, when 128-byte writing is performed 16 times for different addresses in 2-

Kbyte block and then the entire block is erased, the rewrite/erase cycle is counted as one. However, writing to the same address

for several times as one erasing is not enabled (overwriting is prohibited).

Note 2. This indicates the minimum number that guarantees the characteristics after rewriting. (The guaranteed value is in the range

from one to the minimum number.)

Note 3. This indicates the characteristic when rewrite is performed within the specification range including the minimum number.

Table 5.20

Data Flash (Flash Memory for Data Storage) Characteristics

Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.

Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC

Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC

Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC

Temperature range for the programming/erasure operation:

Ta = -40 to +85°C. Ta is the same under conditions 1 to 3.

Item

Symbol

Min.

Typ.

Max.

Unit

Test Conditions

Programming time

8 bytes

tDP8

-0.4

PCLK =

50 MHz

128 bytes

tDP128

-1

Erasure time

2 Kbytes

tDE2K

250

PCLK =

50 MHz

Blank check time

8 bytes

tDBC8

sPCLK =

50 MHz

2 Kbytes

tDBC2K

0.7

Rewrite/erase cycle*1

NDPEC

30000*2

Times

Suspend delay time during writing

tDSPD

120

s

Figure 5.24

PCLK =

50 MHz

First suspend delay time during erasing

(in suspend priority mode)

tDSESD1

120

s

Second suspend delay time during

erasing (in suspend priority mode)

tDSESD2

1.7

Suspend delay time during erasing

(in erasure priority mode)

tDSEED

1.7

Data hold time*3

tDDRP

Year

R5F562TADDFM Datasheet(PDF) 86 Page - Renesas Technology Corp

R5F562TADDFM Datasheet(HTML) 86 Page - Renesas Technology Corp

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94

Datasheet Download

Link URL