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R5F562TADDFM Datasheet(PDF) 48 Page - Renesas Technology Corp |
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R5F562TADDFM Datasheet(HTML) 48 Page - Renesas Technology Corp |
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48 / 94 page  R01DS0096EJ0100 Rev.1.00 Page 48 of 92 Apr 20, 2011 RX62T Group 4. I/O Registers 0009 4004h LIN0 LIN self-test control register LSTC 8 8 2 to 3PCLK*5 0009 4008h LIN0 Mode register L0MD 8 8, 16, 32 2 to 3PCLK*5 0009 4009h LIN0 Break field setting register L0BRK 8 8, 16, 32 2 to 3PCLK*5 0009 400Ah LIN0 Space setting register L0SPC 8 8, 16, 32 2 to 3PCLK*5 0009 400Bh LIN0 Wake-up setting register L0WUP 8 8, 16, 32 2 to 3PCLK*5 0009 400Ch LIN0 Interrupt enable register L0IE 8 8, 16 2 to 3PCLK*5 0009 400Dh LIN0 Error detection enable register L0EDE 8 8, 16 2 to 3PCLK*5 0009 400Eh LIN0 Control register L0C 8 8 2 to 3PCLK*5 0009 4010h LIN0 Transmission control register L0TC 8 8, 16, 32 2 to 3PCLK*5 0009 4011h LIN0 Mode status register L0MST 8 8, 16, 32 2 to 3PCLK*5 0009 4012h LIN0 Status register L0ST 8 8, 16, 32 2 to 3PCLK*5 0009 4013h LIN0 Error status register L0EST 8 8, 16, 32 2 to 3PCLK*5 0009 4014h LIN0 Response field set register L0RFC 8 8, 16 2 to 3PCLK*5 0009 4015h LIN0 Buffer register L0IDB 8 8, 16 2 to 3PCLK*5 0009 4016h LIN0 Check sum buffer register L0CBR 8 8 2 to 3PCLK*5 0009 4018h LIN0 Data 1 buffer register L0DB1 8 8, 16, 32 2 to 3PCLK*5 0009 4019h LIN0 Data 2 buffer register L0DB2 8 8, 16, 32 2 to 3PCLK*5 0009 401Ah LIN0 Data 3 buffer register L0DB3 8 8, 16, 32 2 to 3PCLK*5 0009 401Bh LIN0 Data 4 buffer register L0DB4 8 8, 16, 32 2 to 3PCLK*5 0009 401Ch LIN0 Data 5 buffer register L0DB5 8 8, 16, 32 2 to 3PCLK*5 0009 401Dh LIN0 Data 6 buffer register L0DB6 8 8, 16, 32 2 to 3PCLK*5 0009 401Eh LIN0 Data 7 buffer register L0DB7 8 8, 16, 32 2 to 3PCLK*5 0009 401Fh LIN0 Data 8 buffer register L0DB8 8 8, 16, 32 2 to 3PCLK*5 000C 1200h MTU3 Timer control register TCR 8 8, 16, 32 5ICLK 000C 1201h MTU4 Timer control register TCR 8 8 5ICLK 000C 1202h MTU3 Timer mode register 1 TMDR1 8 8, 16 5ICLK 000C 1203h MTU4 Timer mode register 1 TMDR1 8 8 5ICLK 000C 1204h MTU3 Timer I/O control register H TIORH 8 8, 16, 32 5ICLK 000C 1205h MTU3 Timer I/O control register L TIORL 8 8 5ICLK 000C 1206h MTU4 Timer I/O control register H TIORH 8 8, 16 5ICLK 000C 1207h MTU4 Timer I/O control register L TIORL 8 8 5ICLK 000C 1208h MTU3 Timer interrupt enable register TIER 8 8, 16 5ICLK 000C 1209h MTU4 Timer interrupt enable register TIER 8 8 5ICLK 000C 120Ah MTU Timer output master enable register A TOERA 8 8 5ICLK 000C 120Dh MTU Timer gate control register A TGCRA 8 8 5ICLK 000C 120Eh MTU Timer output control register 1A TOCR1A 8 8, 16 5ICLK 000C 120Fh MTU Timer output control register 2A TOCR2A 8 8 5ICLK 000C 1210h MTU3 Timer counter TCNT 16 16, 32 5ICLK 000C 1212h MTU4 Timer counter TCNT 16 16 5ICLK 000C 1214h MTU Timer cycle data register A TCDRA 16 16, 32 5ICLK 000C 1216h MTU Timer dead time data register A TDDRA 16 16 5ICLK 000C 1218h MTU3 Timer general register A TGRA 16 16, 32 5ICLK 000C 121Ah MTU3 Timer general register B TGRB 16 16 5ICLK 000C 121Ch MTU4 Timer general register A TGRA 16 16, 32 5ICLK Table 4.1 List of I/O Registers (Address Order) (15 / 23) Address Module Abbreviation Register Name Register Abbreviation Number of Bits Access Size Number of Access Cycles |
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