R5F562TADDFM datasheet(76/94 Pages) RENESAS

76 / 94 page

R01DS0096EJ0100 Rev.1.00

Page 76 of 92

Apr 20, 2011

RX62T Group

5. Electrical Characteristics

Note: • tIcyc: ICLK cycle

Figure 5.16

MTU3 Input/Output Timing

Figure 5.17

MTU3 Clock Input Timing

Table 5.11

Timing of On-Chip Peripheral Modules (4)

Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.

Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC

Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC

Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC

Ta =

40 to +85C. Ta is the same under conditions 1 to 3.

Item

Symbol

Min.

Max.

Unit

Test

Conditions

MTU3

Input capture input pulse width

(single-edge setting)

tTICW

3.0

tIcyc

Figure 5.16

Input capture input pulse width

(both-edge setting)

tTICW

5.0

tIcyc

Timer clock pulse width

(single-edge setting)

tTCKWH/L

3.0

tIcyc

Figure 5.17

Timer clock pulse width

(both-edge setting)

tTCKWH/L

5.0

tIcyc

Timer clock pulse width

(phase coefficient mode)

tTCKWH/L

5.0

tIcyc

GPT

Input capture input pulse width

(single-edge setting)

tGTICW

3.0

tIcyc

Figure 5.18

Input capture input pulse width

(both-edge setting)

tGTICW

5.0

tIcyc

Input capture

input

ICLK

tTICW

MTCLKA to

MTCLKD

ICLK

tTCKWL

tTCKWH

R5F562TADDFM Datasheet(PDF) 76 Page - Renesas Technology Corp

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