R5F562TADDFM datasheet(64/94 Pages) RENESAS

64 / 94 page

R01DS0096EJ0100 Rev.1.00

Page 64 of 92

Apr 20, 2011

RX62T Group

5. Electrical Characteristics

5.3

AC Characteristics

5.3.1

Clock Timing

Table 5.5

Operation Frequency Value

Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.

Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC

Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC

Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC

Ta = -40 to +85°C. Ta is the same under conditions 1 to 3.

Item

Symbol

Min.

Typ.

Max.

Unit

Operating

frequency

System clock (ICLK)

100

MHz

Peripheral module clock (PCLK)

Table 5.6

Clock Timing

Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.

Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC

Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC

Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V

AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC

Ta =

40 to +85C. Ta is the same under conditions 1 to 3.

Item

Symbol

Min.

Max.

Unit

Test

Conditions

Oscillation settling time after reset (crystal)

tOSC1

Figure 5.1

Oscillation settling time after leaving software standby mode

(crystal)

tOSC2

Figure 5.2

Oscillation settling time after leaving deep software standby

mode (crystal)

tOSC3

Figure 5.3

EXTAL external clock output delay settling time

tDEXT

Figure 5.1

EXTAL external clock input low pulse width

tEXL

Figure 5.4

EXTAL external clock input high pulse width

tEXH

EXTAL external clock rising time

tEXr

-5

EXTAL external clock falling time

tEXf

-5

On-chip oscillator (IWDTCLK) oscillation frequency

fIWDTCLK

62.5

187.5

kHz

R5F562TADDFM Datasheet(PDF) 64 Page - Renesas Technology Corp

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