| Electronic Components Datasheet Search |
|
R5F562TADDFM Datasheet(PDF) 72 Page - Renesas Technology Corp |
|
|
|||||||||||||||||||||||||||||
R5F562TADDFM Datasheet(HTML) 72 Page - Renesas Technology Corp |
|
72 / 94 page ![]() R01DS0096EJ0100 Rev.1.00 Page 72 of 92 Apr 20, 2011 RX62T Group 5. Electrical Characteristics Note: • Note 1: tPcyc: PCLK cycle Table 5.10 Timing of On-Chip Peripheral Modules (3) Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3. Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC Ta = 40 to +85C. Ta is the same under conditions 1 to 3. Item Symbol Min. Max. Unit Test Conditions RSPI RSPCK clock cycle Master tSPcyc 4 4096 tPcyc Figure 5.11 Slave 8 4096 RSPCK clock high pulse width Master tSPCKWH (tSpcyc - tSPCKR - tSPCKF) / 2-3 -ns Slave (tSpcyc - tSPCKR - tSPCKF) / 2 - RSPCK clock low pulse width Master tSPCKWL (tSpcyc - tSPCKR - tSPCKF) / 2-3 -ns Slave (tSpcyc - tSPCKR - tSPCKF) / 2 - RSPCK clock rise/fall time Output tSPCKR tSPCKF -5 ns Input - 1 s Data input setup time Master tSU 25 - ns Figure 5.12 to Figure 5.15 Slave 0 - Data input hold time Master tH 0- ns Slave 20+2 t Pcyc - SSL setup time Master tLEAD 18 tSPcyc Slave 4 - tPcyc SSL hold time Master tLAG 18 tSPcyc Slave 4 - tPcyc Data output delay time Master tOD -20 ns Slave - 3 t Pcyc +40 Data output hold time Master tOH 0- ns Slave 0 - Sucessive transmission delay time Master tTD tSPcyc+2tPcyc 8 t SPcyc +2 t Pcyc ns Slave 4 t Pcyc - MOSI, MISO rise/fall time Output tDR tDF - 15 ns Figure 5.12 to Figure 5.15 Input - 1 s SSL rise/fall time Output tSSLR tSSLF -15 ns Input - 1 s Slave access time tSA -4 tPcyc Figure 5.12 to Figure 5.15 Slave output release time tREL -3 tPcyc |
|
Link URL |
| Does ALLDATASHEET help your business so far? [ DONATE ] |
About Alldatasheet | Advertisement | Contact us | Privacy Policy | Link to Datasheet | Link Exchange | Manufacturer List All Rights Reserved©Alldatasheet.com |
| Russian : Alldatasheetru.com | Korean : Alldatasheet.co.kr | Spanish : Alldatasheet.es | French : Alldatasheet.fr | Italian : Alldatasheetit.com Portuguese : Alldatasheetpt.com | Polish : Alldatasheet.pl | Vietnamese : Alldatasheet.vn Indian : Alldatasheet.in | Mexican : Alldatasheet.com.mx | British : Alldatasheet.co.uk | New Zealand : Alldatasheet.co.nz |
|
Family Site : ic2ic.com |
icmetro.com |