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R5F562TADDFM Datasheet(PDF) 82 Page - Renesas Technology Corp

Part # R5F562TADDFM
Description  100-MHz 32-bit RX MCUs, FPU, 165 DMIPS, 12-bit ADC
PDF  94 Pages
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Manufacturer  RENESAS [Renesas Technology Corp]
Direct Link  http://www.renesas.com
Logo RENESAS - Renesas Technology Corp

R5F562TADDFM Datasheet(HTML) 82 Page - Renesas Technology Corp

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R01DS0096EJ0100 Rev.1.00
Page 82 of 92
Apr 20, 2011
RX62T Group
5. Electrical Characteristics
5.5
Power-on Reset Circuit, Voltage Detection Circuit Characteristics
Note 1. The power-off time indicates the time when VCC is below the minimum value of voltage detection levels VPOR, Vdet1, and Vdet2
for the POR/ LVD.
Figure 5.20
Power-on Reset Timing
Table 5.17
Power-on Reset Circuit, Voltage Detection Circuit Characteristics
Note:Items for which test conditions are not specifically stated in the table below have the same values under conditions 1 to 3.
Condition 1: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 3.0 to 3.6 V, VREFH0 = 3.0 V to AVCC0, VREF = 3.0 V to AVCC
Condition 2: VCC = PLLVCC = 2.7 to 3.6 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Ta = -40 to +85°C. Ta is the same under conditions 1 to 3.
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Voltage detection
level
Power-on reset (POR)
VPOR
2.48
2.60
2.72
V
Figure 5.20
Voltage detection circuit
(LVD)
Vdet1
2.68
2.80
2.92
Figure 5.21
Vdet2
2.98
3.10
3.22
Figure 5.22
Internal reset time
tPOR
20
35
50
ms
Figure 5.21 and
Figure 5.22
Min. VCC down time*1
tVOFF
200
-
-
us
Figure 5.20 to
Figure 5.22
Reply delay time
tdet
-
-
200
us
Condition 3: VCC = PLLVCC = 4.0 to 5.5 V, VSS = PLLVSS = AVSS0 = AVSS = VREFL0 = 0 V
AVCC0 = AVCC = 4.0 to 5.5 V, VREFH0 = 4.0 V to AVCC0, VREF = 4.0 V to AVCC
Ta = -40 to +85°C
Item
Symbol
Min.
Typ.
Max.
Unit
Test Conditions
Voltage detection
level
Power-on reset (POR)
VPOR
3.70
3.90
4.10
V
Figure 5.20
Voltage detection circuit
(LVD)
Vdet1
3.95
4.15
4.35
Figure 5.21
Vdet2
4.40
4.60
4.80
Figure 5.22
Internal reset time
tPOR
20
35
50
ms
Figure 5.21 and
Figure 5.22
Min. VCC down time*1
tVOFF
200
-
-
us
Figure 5.20 to
Figure 5.22
Reply delay time
tdet
-
-
200
us
Internal reset signal
(low valid)
VCC
t VOFF
VPOR
t POR
t POR
tdet



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