LPC810M021FN8 datasheet(43/313 Pages) NXP

43 / 313 page

UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

43 of 313

NXP Semiconductors

UM10601

Chapter 5: LPC800 Reduced power modes and Power Management

5.6 Register description

Table 41.

Wake-up sources for reduced power modes

Power mode

Wake-up source

Conditions

Sleep

Any interrupt

Enable interrupt in NVIC.

Deep-sleep and

Power-down

Pin interrupts

Enable pin interrupts in NVIC and STARTERP0 registers.

BOD interrupt

• Enable interrupt in NVIC and STARTERP1 registers.

• Enable interrupt in BODCTRL register.

• BOD powered in PDSLEEPCFG register.

BOD reset

• Enable reset in BODCTRL register.

• BOD powered in PDSLEEPCFG register.

WWDT interrupt

• Enable interrupt in NVIC and STARTERP1 registers.

• WWDT running. Enable WWDT in WWDT MOD register and feed.

• Enable interrupt in WWDT MOD register.

• WDOsc powered in PDSLEEPCFG register.

WWDT reset

• WWDT running.

• Enable reset in WWDT MOD register.

• WDOsc powered in PDSLEEPCFG register.

Self Wake-up Timer

(WKT) time-out

• Enable interrupt in NVIC and STARTERP1 registers.

• Enable low-power oscillator in the GPREG4 register in the PCON block.

• Select low-power clock for WKT clock in the WKT CTRL register.

• Start the WKT by writing a time-out value to the WKT COUNT register.

Interrupt from

USART/SPI/I2C

peripheral

• Enable interrupt in NVIC and STARTERP1 registers.

• Enable USART/I2C/SPI interrupts.

• Provide an external clock signal to the peripheral.

• Configure the USART in synchronous slave mode and I2C and SPI in

slave mode.

Deep power-down WAKEUP pin PIO0_4 Enable the WAKEUP function in the GPREG4 register in the PMU.

WKT time-out

• Enable the low-power oscillator in the GPREG4 register in the PMU.

• Enable the low-power oscillator to keep running in Deep power-down

mode in the GPREG4 register in the PMU.

• Select low-power clock for WKT clock in the WKT CTRL register.

• Start WKT by writing a time-out value to the WKT COUNT register.

Table 42.

Name

Access

Address

offset

Description

Reset

value

Reference

PCON

R/W

0x000

Power control register

0x0

Table 43

GPREG0

R/W

0x004

General purpose register 0

0x0

Table 44

GPREG1

R/W

0x008

General purpose register 1

0x0

Table 44

GPREG2

R/W

0x00C

General purpose register 2

0x0

Table 44

GPREG3

R/W

0x010

General purpose register 3

0x0

Table 44

DPDCTRL

R/W

0x014

Deep power-down control

0x0

Table 45

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