LPC810M021FN8 datasheet(65/313 Pages) NXP

65 / 313 page

UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

65 of 313

NXP Semiconductors

UM10601

Chapter 6: LPC800 I/O configuration (IOCON)

6.5.8 PIO0_11 register

Table 56.

PIO0_11 register (PIO0_11, address 0x4004 401C) bit description

Bit

Symbol

Value

Description

Reset

value

5:0

Reserved.

INV

Invert input

Input not inverted (HIGH on pin reads as 1; LOW on pin

reads as 0).

Input inverted (HIGH on pin reads as 0, LOW on pin reads

as 1).

Reserved.

9:8

I2CMODE

Selects I2C mode.

Select Standard mode (I2CMODE = 00, default) or

Standard I/O functionality (I2CMODE = 01) if the pin

function is GPIO (FUNC = 000).

0x0

Standard mode/ Fast-mode I2C.

0x1

Standard I/O functionality

0x2

Fast-mode Plus I2C

0x3

Reserved.

12:11

S_MODE

Digital filter sample mode.

0x0

Bypass input filter.

0x1

1 clock cycle. Input pulses shorter than one filter clock are

rejected.

0x2

2 clock cycles. Input pulses shorter than two filter clocks

are rejected.

0x3

3 clock cycles. Input pulses shorter than three filter clocks

are rejected.

15:13 CLK_DIV

Select peripheral clock divider for input filter sampling

clock. Value 0x7 is reserved.

0x0

IOCONCLKDIV0.

0x1

IOCONCLKDIV1.

0x2

IOCONCLKDIV2.

0x3

IOCONCLKDIV3.

0x4

IOCONCLKDIV4.

0x5

IOCONCLKDIV5.

0x6

IOCONCLKDIV6.

31:16 -

Reserved.

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