LPC810M021FN8 datasheet(10/313 Pages) NXP

10 / 313 page

UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

10 of 313

3.1 How to read this chapter

The NVIC is identical on all LPC800 parts.

The SPI1 and USART2 interrupts are implemented on parts LPC812M101FDH20 and

LPC812M101FDH16 only.

3.2 Features

• Nested Vectored Interrupt Controller that is an integral part of the ARM Cortex-M0+.

• Tightly coupled interrupt controller provides low interrupt latency.

• Controls system exceptions and peripheral interrupts.

• The NVIC supports 32 vectored interrupts.

• Four programmable interrupt priority levels with hardware priority level masking.

• Software interrupt generation using the ARM exceptions SVCall and PendSV.

• Support for NMI.

• ARM Cortex M0+ Vector table offset register VTOR implemented.

3.3 General description

The Nested Vectored Interrupt Controller (NVIC) is an integral part of the Cortex-M0+. The

tight coupling to the CPU allows for low interrupt latency and efficient processing of late

arriving interrupts.

3.3.1 Interrupt sources

Table 3 lists the interrupt sources for each peripheral function. Each peripheral device

may have one or more interrupt lines to the Vectored Interrupt Controller. Each line may

represent more than one interrupt source. The interrupt number does not imply any

interrupt priority.

See Ref. 1 for a detailed description of the NVIC and the NVIC register description.

UM10601

Chapter 3: LPC800 Nested Vectored Interrupt Controller

(NVIC)

Rev. 1.0 — 7 November 2012

Preliminary user manual

Table 3.

Connection of interrupt sources to the NVIC

Interrupt

number

Name

Description

Flags

SPI0_IRQ

SPI0 interrupt

See Table 192 “SPI Interrupt Enable read and Set register

(INTENSET, addresses 0x4005 800C (SPI0) , 0x4005 C00C

(SPI1)) bit description”.

SPI1_IRQ

SPI1 interrupt

Same as SPI0_IRQ

Reserved

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