LPC810M021FN8 datasheet(57/313 Pages) NXP

57 / 313 page

UM10601

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Preliminary user manual

Rev. 1.0 — 7 November 2012

57 of 313

NXP Semiconductors

UM10601

Chapter 6: LPC800 I/O configuration (IOCON)

6.5 Register description

Each port pin PIOn_m has one IOCON register assigned to control the pin’s function and

electrical characteristics.

6.5.1 PIO0_17 register

Table 48.

Name

Access

Address

offset

Description

Reset value

Reference

PIO0_17

R/W

0x000

I/O configuration for pin PIO0_17

0x0000 0090

Table 49

PIO0_13

R/W

0x004

I/O configuration for pin PIO0_13

0x0000 0090

Table 50

PIO0_12

R/W

0x008

I/O configuration for pin PIO0_12

0x0000 0090

Table 51

PIO0_5

R/W

0x00C

I/O configuration for pin PIO0_5/RESET 0x0000 0090

Table 52

PIO0_4

R/W

0x010

I/O configuration for pin PIO0_4

0x0000 0090

Table 53

PIO0_3

R/W

0x014

I/O configuration for pin

PIO0_3/SWCLK

0x0000 0090

Table 54

PIO0_2

R/W

0x018

I/O configuration for pin PIO0_2/SWDIO 0x0000 0090

Table 55

PIO0_11

R/W

0x01C

I/O configuration for pin PIO0_11. This

is the pin configuration for the true

open-drain pin.

0x0000 0080

Table 56

PIO0_10

R/W

0x020

I/O configuration for pin PIO0_10. This

is the pin configuration for the true

open-drain pin.

0x0000 0080

Table 57

PIO0_16

R/W

0x024

I/O configuration for pin PIO0_16

0x0000 0090

Table 58

PIO0_15

R/W

0x028

I/O configuration for pin PIO0_15

0x0000 0090

Table 59

PIO0_1

R/W

0x02C

I/O configuration for pin

PIO0_1/ACMP_I1/CLKIN

0x0000 0090

Table 60

0x030

Reserved

PIO0_9

R/W

0x034

I/O configuration for pin

PIO0_9/XTALOUT

0x0000 0090

Table 61

PIO0_8

R/W

0x038

I/O configuration for pin PIO0_8/XTALIN 0x0000 0090

Table 62

PIO0_7

R/W

0x03C

I/O configuration for pin PIO0_7

0x0000 0090

Table 63

PIO0_6

R/W

0x040

I/O configuration for pin

PIO0_6/VDDCMP

0x0000 0090

Table 64

PIO0_0

R/W

0x044

I/O configuration for pin

PIO0_0/ACMP_I0

0x0000 0090

Table 65

PIO0_14

R/W

0x048

I/O configuration for pin PIO0_14

0x0000 0090

Table 66

Table 49.

PIO0_17 register (PIO0_17, address 0x4004 4000) bit description

Bit

Symbol

Value

Description

Reset

value

2:0

Reserved.

LPC810M021FN8 Datasheet(PDF) 57 Page - NXP Semiconductors

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