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WM9714CLGEFL/V Datasheet(PDF) 29 Page - Cirrus Logic

Part # WM9714CLGEFL/V
Description  AC??7 Audio Codec
PDF  120 Pages
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Manufacturer  CIRRUS [Cirrus Logic]
Direct Link  http://www.cirrus.com
Logo CIRRUS - Cirrus Logic

WM9714CLGEFL/V Datasheet(HTML) 29 Page - Cirrus Logic

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WM9714L
Rev 4.0
29
In I2S mode, the MSB is available on the second rising edge of PCMCLK following a PCMFS
transition. The other bits up to the LSB are then transmitted in order. Depending on word length,
PCMCLK frequency and sample rate, there may be unused PCMCLK cycles between the LSB of one
sample and the MSB of the next.
LEFT CHANNEL
RIGHT CHANNEL
PCMFS
PCMCLK
PCMADC/
PCMDAC
1/fs
n
3
2
1
n-2 n-1
LSB
MSB
n
3
2
1
n-2 n-1
LSB
MSB
1 BCLK
1 BCLK
Figure 18 I2S Justified Audio Interface (assuming n-bit word length)
CONTROL
The register bits controlling PCM audio format, word length and operating modes are summarised
below. CTRL must be set to override the normal use of the PCM interface pins as GPIOs, MODE must
be set to specify master/slave modes.
REGISTER
ADDRESS
BIT
LABEL
DEFAULT
DESCRIPTION
36h
PCM
Control
15
CTRL
0
GPIO Pin Configuration Control
0 = GPIO pins as GPIOs
1 = GPIO pins configured as PCM interface
and controlled by this register
14:13
MODE
10
PCM Interface Mode Control
00 = PCM interface disabled [PCMCLK tri-
stated, PCMFS tri-stated]
01 = PCM interface in slave mode [PCMCLK
as input, PCMFS as input]
10 = PCM interface in master mode [PCMCLK
as output, PCMFS as output]
11 = PCM interface in partial master mode
[PCMCLK as output, PCMFS as input]
11:9
DIV
010
PCMCLK Rate Control
000 = Voice DAC clock
001 = Voice DAC clock / 2
010 = Voice DAC clock / 4
011 = Voice DAC clock / 8
100 = Voice DAC clock / 16
All other values are reserved
8
VDACOSR
1
Voice DAC Oversampling Rate Control
0: 128 x fs
1: 64 x fs
7
CP
0
PCMCLK Polarity Control
0 = Normal
1 = Inverted
6
FSP
0
FMT = 00, 01 or 10
FMT = 11
PCMFS Polarity
Control
0 = Normal
1 = Inverted
DSP Mode Control
0 = DSP Mode A
1 = DSP Mode B



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