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PDP83TG720SWCSTQ1 Datasheet(PDF) 33 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 33 Page - Texas Instruments |
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33 / 199 page  7.3.2.3 Test Mode 4 Test mode 4 tests the transmitter distortion. In test mode 4, the DP83TG720S-Q1 will transmit the sequence of symbols generated by Equation 1: g(x) = 1 + x9 + x11 (1) The bit sequences, x0n and x1n, are generated from combinations of the scrambler in accordance to and : 'x0n = Scrn[0] (2) x1n = Scrn[1] ^ Scrn[4] (3) x2n = Scrn[1] ^ Scrn[5] (4) Example streams of the 3-bit nibbles are shown in Table 7-6. Table 7-6. Transmitter Test Mode 4 Symbol Mapping x2n x1n x0n T1n T0n 0 0 0 -1 -1 0 0 1 0 -1 0 1 0 -1 0 0 1 1 -1 +1 1 0 0 +1 0 1 0 1 +1 -1 1 1 0 +1 +1 1 1 1 0 +1 7.3.2.4 Test Mode 5 Test mode 5 tests the transmitter PSD mask. In test mode 5, the DP83TG720S-Q1 will transmit normal Inter- Frame IDLE PAM3 symbols. 7.3.2.5 Test Mode 6 Test mode 6 tests the transmitter droop. In test mode 6, the DP83TG720S-Q1 transmits fifteen {+1} symbols followed by fifteen {-1} symbols with symbol transmission at 750-MHz. This 25-MHz pattern is repeated continuously until the test mode is disabled. 7.3.2.6 Test Mode 7 Test mode 7 enabled bit error rate measurement on a link segment. This mode uses zero data pattern on the MDI to check BER by comparing an expected zero data pattern to any non-zero bit received. Error checking is performed after FEC and 80B/81B decoding. Table 7-7. Test Mode Register Setting MMD Register Value Test Mode MMD1 0x0904 0x2000 Test Mode 1 : Tx_Tclk 125MHz is routed to clkout pin. MMD1 0x0904 0x4000 Test Mode 2 MMD1 0x0904 0x8000 Test Mode 4 : Tx_Tclk 125MHz is routed to clkout pin. MMD1F 0x0453 0x0019 MMD1 0x0904 0xA000 Test Mode 5 MMD1 0x0904 0xC000 Test Mode 6 MMD1 0x0904 0xE000 Test Mode 7 www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 33 |
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