PDP83TG720SWCSTQ1 datasheet(42/199 Pages) TI

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7.4.9 Serial Management Interface

The Serial Management Interface provides access to the DP83TG720S-Q1 internal register space for status

information and configuration. The SMI is compatible with IEEE 802.3 clause 22. The implemented register set

consists of the registers required by the IEEE 802.3 plus several others to provide additional visibility and

controllability of the DP83TG720S-Q1.

The SMI includes the management clock (MDC) and the management input and output data pin (MDIO). MDC is

sourced by the external management entity, also called Station (STA). MDC is not expected to be continuous,

and can be turned off by the external management entity when the bus is idle.

MDIO is sourced by the external management entity and by the PHY. The data on the MDIO pin is latched on the

rising edge of the MDC. MDIO pin requires a pullup resistor (2.2 KΩ), which pulls MDIO high during IDLE and

turnaround.

Up to 9 DP83TG720S-Q1 PHYs can share a common SMI bus. To distinguish between the PHYs, a 3-bit

address is used. During power-up-reset, the DP83TG720S-Q1 latches the PHY_AD configuration pins to

determine its address.

The management entity must not start an SMI transaction in the first cycle after power-up-reset. To maintain

valid operation, the SMI bus must remain inactive at least one MDC cycle after hard reset is deasserted. In

normal MDIO transactions, the register address is taken directly from the management-frame reg_addr field,

thus allowing direct access to 32 16-bit registers (including those defined in IEEE 802.3 and vendor specific).

The data field is used for both reading and writing. The Start code is indicated by a <01> pattern. This pattern

makes sure that the MDIO line transitions from the default idle line state. Turnaround is defined as an idle bit

time inserted between the Register Address field and the Data field. To avoid contention during a read

transaction, no device may actively drive the MDIO signal during the first bit of turnaround. The addressed

DP83TG720S-Q1 drives the MDIO with a zero for the second bit of turnaround and follows this with the required

data.

For write transactions, the station-management entity writes data to the addressed DP83TG720S-Q1, thus

eliminating the requirement for MDIO Turnaround. The turnaround time is filled by the management entity by

inserting <10>.

Table 7-13. SMI Protocol Structure

SMI PROTOCOL

Read Operation

Write Operation

7.4.10 Direct Register Access

Direct register access can be used for the first 31 registers (0x0h through 0x1Fh).

7.4.11 Extended Register Space Access

The DP83TG720S-Q1 SMI function supports read and write access to the extended register set using registers

REGCR (0x000Dh) and ADDAR (0x000Eh) and the MDIO Manageable Device (MMD) indirect method defined in

IEEE 802.3ah Draft for Clause 22 for accessing the Clause 45 extended register set.

REGCR (0x000Dh) is the MDIO Manageable MMD access control. In general, register REGCR[4:0] is the device

address DEVAD that directs any accesses of ADDAR (0x000Eh) register to the appropriate MMD.

The DP83TG720S-Q1 supports 4 MMD device addresses. The 4 MMD register spaces are:

1. DEVAD[4:0] = 11111 (0x1F) is used for IEEE defined registers (0x00 to 0x1F) and vendor specific registers.

This register space is called MMD1F

2. DEVAD[4:0] = 00001 (0x01) is used for 100BASE-T1 PMA MMD register accesses. This register space is

called MMD1.

3. DEVAD[4:0] = 00011 (0x03) is used for vendor specific registers. This register space is called MMD3

4. DEVAD[4:0] = 00111 (0x07) is used for vendor specific registers. This register space is called MMD7

DP83TG720S-Q1

SNLS604 – SEPTEMBER 2020

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