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PDP83TG720SWCSTQ1 Datasheet(PDF) 57 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 57 Page - Texas Instruments |
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57 / 199 page ![]() 7.6.2.2 BMSR Register (Address = 0x1) [reset = 0x141] BMSR is shown in Table 7-25. Return to the Summary Table. Table 7-25. BMSR Register Field Descriptions Bit Field Type Reset Description 15 ieee_100baset4 R 1b0 1 = PHY able to perform 100BASE-T4 0 = PHY not able to perform 100BASE-T4 1b0 = PHY not able to perform 100BASE-T4 1b1 = PHY able to perform 100BASE-T4 14 ieee_100basex_fd R 1b0 1 = PHY able to perform full duplex 100BASE-X 0 = PHY not able to perform full duplex 100BASE-X 1b0 = PHY not able to perform full duplex 100BASE-X 1b1 = PHY able to perform full duplex 100BASE-X 13 ieee_100basex_hd R 1b0 1 = PHY able to perform half duplex 100BASE-X 0 = PHY not able to perform half duplex 100BASE-X 1b0 = PHY not able to perform half duplex 100BASE-X 1b1 = PHY able to perform half duplex 100BASE-X 12 ieee_10mb_fd R 1b0 1 = PHY able to operate at 10 Mb/s in full duplex mode 0 = PHY not able to operate at 10 Mb/s in full duplex mode 1b0 = PHY not able to operate at 10 Mb/s in full duplex mode 1b1 = PHY able to operate at 10 Mb/s in full duplex mode 11 ieee_10mb_hd R 1b0 1 = PHY able to operate at 10 Mb/s in half duplex mode 0 = PHY not able to operate at 10 Mb/s in half duplex mode 1b0 = PHY not able to operate at 10 Mb/s in half duplex mode 1b1 = PHY able to operate at 10 Mb/s in half duplex mode 10 ieee_100baset2_fd R 1b0 1 = PHY able to perform full duplex 100BASE-T2 0 = PHY not able to perform full duplex 100BASE-T2 1b0 = PHY not able to perform full duplex 100BASE-T2 1b1 = PHY able to perform full duplex 100BASE-T2 9 ieee_100baset2_hd R 1b0 1 = PHY able to perform half duplex 100BASE-T2 0 = PHY not able to perform half duplex 100BASE-T2 1b0 = PHY not able to perform half duplex 100BASE-T2 1b1 = PHY able to perform half duplex 100BASE-T2 8 extended_status R 1b1 Extended staus in register 0xf 1b0 = No extended status information in Register 15 1b1 = Extended status information in Register 15 7 unidirectional_ability R 1b0 Reserved 6 preamble_supression R 1b1 MF preamble supression 1b0 = PHY will not accept management frames with preamble suppressed 1b1 = PHY will accept management frames with preamble suppressed. 5 aneg_complete R 1b0 Reserved www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 57 |
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