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PDP83TG720SWCSTQ1 Datasheet(PDF) 14 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 14 Page - Texas Instruments |
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14 / 199 page  (1) PARAMETER TEST CONDITIONS MIN NOM MAX UNIT SSD symbol on MDI to Rising edge of RGMII RX_CLK with assertion of RX_CTRL (RS-FEC bypass mode) 400 ns SSD symbol on MDI to first symbol of SGMII 9 µs SSD symbol on MDI to first symbol of SGMII (RS-FEC bypass mode) 450 ns TRANSMIT LATENCY TIMING RGMII Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI 8 µs RGMII Rising edge TX_CLK with assertion TX_CTRL to SSD symbol on MDI (RS-FEC bypass mode) 600 ns First symbol of SGMII to SSD symbol on MDI 9 µs First symbol of SGMII to SSD symbol on MDI (RS-FEC bypass mode) 700 ns 25 MHz OSCILLATOR REQUIREMENTS Frequency (XI) 25 MHz Frequency Tolerance and Stability Over temperature and aging –100 100 ppm Rise / Fall Time (10% - 90%) 8 ns Jitter (RMS) 3.6 ps Duty Cycle 50 % RGMII TIMING TsetupR TX_D[3:0], TX_CTRL Setup to TX_CLK on PHY pins 1 2 ns TholdR TX_D[3:0], TX_CTRL Hold from TX_CLK (5) on PHY pins 1 2 ns TskewT RX_D[3:0], RX_CTRL Delay from RX_CLK (Align Mode Enabled) On PHY Pins -500 0 500 ps TskewT (Shift) RX_D[3:0], RX_CTRL Delay from RX_CLK (Shift Mode Enabled, default)(4) On PHY Pins 2.240 2.650 2.970 ns Tcyc Clock Cycle Duration RX_CLK 7.2 8 8.8 ns Tcyc Clock Cycle Duration TX_CLK 7.2 8 8.8 ns Duty_G Duty Cycle RX_CLK 45 50 55 % Duty_G Duty Cycle TX_CLK 45 50 55 % Tr Rise Time (20% - 80%) CL=Ctrace=5pF 0.75 ns Tf Fall Time (20% - 80%) CL=Ctrace = 5pF 0.75 ns RGMII Shift Mode Delays DLL DLL_RX_DELAY_CTRL_SL=0(4) 0.330 0.650 0.970 ns DLL DLL_RX_DELAY_CTRL_SL=1(4) 0.580 0.900 1.220 ns DLL DLL_RX_DELAY_CTRL_SL=2(4) 0.830 1.150 1470 ns DLL DLL_RX_DELAY_CTRL_SL=3(4) 1.080 1.400 1.720 ns DLL DLL_RX_DELAY_CTRL_SL=4(4) 1.240 1.650 1.970 ns DLL DLL_RX_DELAY_CTRL_SL=5(4) 1.490 1.990 2.220 ns DLL DLL_RX_DELAY_CTRL_SL=6(4) 1.740 2.150 2.470 ns DLL DLL_RX_DELAY_CTRL_SL=7(4) 1.990 2.400 2.730 ns DLL DLL_RX_DELAY_CTRL_SL=8(4) 2.240 2.650 2.970 ns DLL DLL_RX_DELAY_CTRL_SL=9(4) 2.490 2.900 3.220 ns SGMII TRANSMITTER AC TIMING Clock signal duty cycle at 625 MHz 48 52 % Trise Vod Rise Time 100 200 ps DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 www.ti.com 14 Submit Document Feedback Copyright © 2020 Texas Instruments Incorporated |
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