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PDP83TG720SWCSTQ1 Datasheet(PDF) 65 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 65 Page - Texas Instruments |
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65 / 199 page  7.6.2.9 MII_REG_13 Register (Address = 0x13) [reset = 0x0] MII_REG_13 is shown in Table 7-32. Return to the Summary Table. Table 7-32. MII_REG_13 Register Field Descriptions Bit Field Type Reset Description 15 under_volt_int R 1b0 Under volt interrupt status 14 over_volt_int R 1b0 Over volt interrupt status 13 RESERVED R 1b0 Reserved 12 RESERVED R 1b0 Reserved 11 over_temp_int R 1b0 Over temp interrupt status 10 sleep_int R 1b0 Sleep mode change interrupt status 9 pol_change_int R 1b0 Data polarity change interrupt status 8 not_one_hot_int R 1b0 Not one hot interrupt status 7 under_volt_int_en R/W 1b0 Under volt interrupt enable 6 over_volt_int_en R/W 1b0 Over volt interrupt enable 5 unused_int_6 R/W 1b0 Reserved 4 unused_int_5 R/W 1b0 Reserved 3 over_temp_int_en R/W 1b0 Over temp interrupt enable 2 sleep_int_en R/W 1b0 Sleep mode change interrupt enable 1 pol_change_int_en R/W 1b0 Data Polarity change interrupt enable 0 not_one_hot_int_en R/W 1b0 Not one hot interrupt enable www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 65 |
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