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PDP83TG720SWCSTQ1 Datasheet(PDF) 69 Page - Texas Instruments |
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PDP83TG720SWCSTQ1 Datasheet(HTML) 69 Page - Texas Instruments |
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69 / 199 page ![]() 7.6.2.13 MII_REG_1E Register (Address = 0x1E) [reset = 0x0] MII_REG_1E is shown in Table 7-36. Return to the Summary Table. Table 7-36. MII_REG_1E Register Field Descriptions Bit Field Type Reset Description 15 tdr_start R/WMC 1b0 Start TDR manually 1b0 = No TDR 1b1 = TDR start 14 cfg_tdr_auto_run R/W 1b0 Enable TDR auto run on link down 1b0 = TDR start manually 1b1 = TDR start automatically on link down 13-2 RESERVED R 12b0000000 00000 Reserved 1 tdr_done R 1b0 TDR done status 0 tdr_fail R 1b0 TDR fail status www.ti.com DP83TG720S-Q1 SNLS604 – SEPTEMBER 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 69 |
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